verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots

jitter_eliminate
................\Screenshot.png
................\jitter_eliminate-tb.v~
................\jitter_eliminate-filelist.txt~
................\jitter_eliminate.v
................\jitter_eliminate-filelist.txt
................\jitter_eliminate.vvp
................\jitter_eliminate-tb.v
................\jitter_eliminate.vcd
................\jitter_eliminate.v~

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