Xilinx Inc. 1 wire interface to HDL source code, can be used to read the 1 wire in the rom.

README
vhdl\bitreg.vhd
....\bytereg.vhd
....\clk_div.vhd
....\crcreg.vhd
....\jcounter.vhd
....\onewire_iface.vhd
....\onewire_iface_syn.prj
....\onewire_master.vhd
....\shreg.vhd
....\TEST_ONEWIRE_IFACE.DO
....\TEST_ONEWIRE_IFACE.VHD
vhdl
.erilog\bitreg.v
.......\clk_div.v
.......\crcreg.v
.......\defines.v
.......\glbl.v
.......\jcnt1.v
.......\jcnt2.v
.......\onewire_iface.v
.......\onewire_iface_syn.prj
.......\onewire_master.v
.......\parallel_sn_data.v
.......\sr1.v
.......\sr2.v
.......\TEST_NO_SLAVE.do
.......\TEST_NO_SLAVE.v
.......\TEST_ONEWIRE_WITH_BAD_CRC.do
.......\TEST_ONEWIRE_WITH_BAD_CRC.v
.......\TEST_ONEWIRE_WITH_VALID_CRC.do
.......\TEST_ONEWIRE_WITH_VALID_CRC.v
.......\TEST_SLAVE_PRESENT.do
.......\TEST_SLAVE_PRESENT.v
verilog
xapp198[1].pdf

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．