verilog description of the Ethernet MAC layer source code, function correctly, has been tested in the FPGA development board! Need to hurry the next! ! !

verilog\mgmt\management_top.v
.......\....\manage_registers.v
.......\....\mdio.v
.......\rx_engine\counter.v
.......\.........\CRC32_D64.v
.......\.........\CRC32_D8.v
.......\.........\rxClkgen.v
.......\.........\rxCRC.v
.......\.........\rxDAchecker.v
.......\.........\rxDataPath.v
.......\.........\rxLenTypChecker.v
.......\.........\rxLinkFaultState.v
.......\.........\rxNumCounter.v
.......\.........\rxReceiveEngine.ucf
.......\.........\rxReceiveEngine.v
.......\.........\rxRSIO.v
.......\.........\rxRSLayer.v
.......\.........\rxStateMachine.v
.......\.........\rxStatModule.v
.......\.........\SwitchAsyncFIFO.v
.......\.........\SwitchSyncFIFO.v
.......\.........\timescale.v
.......\.........\xgiga_define.v
.......\tx_engine\ack_counter.v
.......\.........\byte_counter.v
.......\.........\CRC32_D64.v
.......\.........\CRC32_D8.v
.......\.........\TransmitTop.v
.......\mgmt
.......\rx_engine
.......\tx_engine
verilog

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