The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc script, the output report.

fft64(方琳&沈翔&魏鹏)\doc\64 Points FFT Processor.doc
.....................\report\area.rpt
.....................\......\design.rpt
.....................\......\power.rpt
.....................\......\timing.rpt
.....................\......\timing_violators.rpt
.....................\script\fft64.tcl
.....................\.rc\bm.v
.....................\...\booth.v
.....................\...\butterfly.v
.....................\...\cl42_20.v
.....................\...\cla20.v
.....................\...\clk_div.v
.....................\...\complex_mul.v
.....................\...\control.v
.....................\...\csa_13.v
.....................\...\csa_15.v
.....................\...\dataout.v
.....................\...\delay1.v
.....................\...\delay16.v
.....................\...\delay2.v
.....................\...\delay4.v
.....................\...\delay8.v
.....................\...\dff.v
.....................\...\fft64.v
.....................\...\FFT_r\FFT_r\bm.v
.....................\...\.....\.....\bm.v.bak
.....................\...\.....\.....\butterfly.v
.....................\...\.....\.....\butterfly.v.bak
.....................\...\.....\.....\clk_div.v
.....................\...\.....\.....\clk_div.v.bak
.....................\...\.....\.....\complex_mul.v
.....................\...\.....\.....\complex_mul.v.bak
.....................\...\.....\.....\control.v
.....................\...\.....\.....\control.v.bak
.....................\...\.....\.....\data\din_im.txt
.....................\...\.....\.....\....\din_re.txt
.....................\...\.....\.....\dataout.v
.....................\...\.....\.....\dataout.v.bak
.....................\...\.....\.....\delay1.v
.....................\...\.....\.....\delay1.v.bak
.....................\...\.....\.....\delay16.v
.....................\...\.....\.....\delay16.v.bak
.....................\...\.....\.....\delay2.v
.....................\...\.....\.....\delay2.v.bak
.....................\...\.....\.....\delay4.v
.....................\...\.....\.....\delay4.v.bak
.....................\...\.....\.....\delay8.v
.....................\...\.....\.....\delay8.v.bak
.....................\...\.....\.....\dff.v
.....................\...\.....\.....\dff.v.bak
.....................\...\.....\.....\FFT.cr.mti
.....................\...\.....\.....\FFT.mpf
.....................\...\.....\.....\fft64.v
.....................\...\.....\.....\fft64.v.bak
.....................\...\.....\.....\input_buffer.v
.....................\...\.....\.....\input_buffer.v.bak
.....................\...\.....\.....\inverter.v
.....................\...\.....\.....\inverter.v.bak
.....................\...\.....\.....\multiplier.v
.....................\...\.....\.....\multiplier.v.bak
.....................\...\.....\.....\result_out.txt
.....................\...\.....\.....\switch1.v
.....................\...\.....\.....\switch1.v.bak
.....................\...\.....\.....\switch16.v
.....................\...\.....\.....\switch16.v.bak
.....................\...\.....\.....\switch2.v
.....................\...\.....\.....\switch2.v.bak
.....................\...\.....\.....\switch4.v
.....................\...\.....\.....\switch4.v.bak
.....................\...\.....\.....\switch8.v
.....................\...\.....\.....\switch8.v.bak
.....................\...\.....\.....\tb_fft64.v
.....................\...\.....\.....\tb_fft64.v.bak
.....................\...\.....\.....\twiddle1.v
.....................\...\.....\.....\twiddle1.v.bak
.....................\...\.....\.....\vsim.wlf
.....................\...\.....\.....\work\bm\verilog.prw
.....................\...\.....\.....\....\..\verilog.psm
.....................\...\.....\.....\....\..\_primary.dat
.....................\...\.....\.....\....\..\_primary.dbs
.....................\...\.....\.....\....\..\_primary.vhd
.....................\...\.....\.....\....\.utterfly\verilog.prw
.....................\...\.....\.....\....\.........\verilog.psm
.....................\...\.....\.....\....\.........\_primary.dat
.....................\...\.....\.....\....\.........\_primary.dbs

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