this is a verilog source code which can count the greatest common divider .

gcd\src\csrc\5NrIB_d.o
...\...\....\5NrI_d.o
...\...\....\5NrI_d.o.incr
...\...\....\BzDP_1_d.o
...\...\....\BzDP_1_d.o.incr
...\...\....\BzDP_1_l.dat
...\...\....\filelist
...\...\....\idincr.db
...\...\....\Makefile
...\...\....\product_timestamp
...\...\....\SIM_l.o
...\...\....\vcsconst.incr
...\...\....\vcspieces.incr
...\...\....\vcstype.incr
...\...\DVEfiles\dve_gui.log
...\...\........\dve_history.log
...\...\........\session.tcl
...\...\gcd_controller.v
...\...\gcd_controller.v~
...\...\gcd_datapath.v
...\...\gcd_datapath.v~
...\...\gcd_input_data
...\...\gcd_testbench.v
...\...\gcd_testbench.v~
...\...\gcd_test_output
...\...\gcd_top.v
...\...\gcd_top.v~
...\...\log
...\...\simv
...\...\.....daidir\.version
...\...\...........\2N5hNe_1.db
...\...\...........\3CjfEb_1.db
...\...\...........\5NrI.tt
...\...\...........\AllModulesSkeletons.db
...\...\...........\b9dpyc_1.db
...\...\...........\BzDP_1.tt
...\...\...........\covg_defs
...\...\...........\didmap.db
...\...\...........\dve_filelist.db
...\...\...........\dve_macro.db
...\...\...........\external_functions
...\...\...........\heZTHe_1.db
...\...\...........\modfilename.db
...\...\...........\mUldHc_1.db
...\...\...........\nCDh3c_1.db
...\...\...........\offfilename.db
...\...\...........\RRrKjd_1.db
...\...\...........\SmwM2c_1.db
...\...\...........\str.db
...\...\...........\topmodules
...\...\...........\vcs_rebuild
...\...\ucli.key
...\...\vcs.key
...\.yn\.synopsys_dc.setup
...\...\.vcsmx_rebuild
...\...\command.log
...\...\default.svf
...\...\EDFF-verilog-verilog.syn
...\...\EDFF-verilog.pvl
...\...\EDFF-verilog.syn
...\...\EDFF.mr
...\...\filenames.log
...\...\gcd_controller-verilog-verilog.syn
...\...\gcd_controller-verilog.pvl
...\...\gcd_controller-verilog.syn
...\...\GCD_CONTROLLER.mr
...\...\gcd_datapath-verilog-verilog.syn
...\...\gcd_datapath-verilog.pvl
...\...\gcd_datapath-verilog.syn
...\...\GCD_DATAPATH.mr
...\...\gcd_testbench-verilog-verilog.syn
...\...\gcd_testbench-verilog.pvl
...\...\gcd_testbench-verilog.syn
...\...\GCD_TESTBENCH.mr
...\...\gcd_top-verilog-verilog.syn
...\...\gcd_top-verilog.pvl
...\...\gcd_top-verilog.syn
...\...\GCD_TOP.mr
...\...\Mux2-verilog-verilog.syn
...\...\Mux2-verilog.pvl
...\...\Mux2-verilog.syn
...\...\MUX2.mr
...\...\Mux3-verilog-verilog.syn
...\...\Mux3-verilog.pvl
...\...\Mux3-verilog.syn
...\...\MUX3.mr
...\...\REDFF-verilog-verilog.syn
...\...\REDFF-verilog.pvl
...\...\REDFF-verilog.syn
...\...\REDFF.mr
...\.rc\csrc
...\...\DVEfiles
...\...\simv.daidir
...\.yn\log
...\...\mapped_db
...\...\netlist
...\...\script
...\...\unmapped_db
...\sim
...\src

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