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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 1kb
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- Author ：jet****
- About ： Nobody
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Introduction - If you have any usage issues, please Google them yourself
Described in the seven-segment code with verilog program, including test file, after quartusii simulation testing and successfully downloaded to the board DE3
Packet file list
(Preview for download)
bin27seg_t.v
bin27seg.v
bin27seg.v
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