Description: Xilinx verilog languages with the platform to achieve single ALU, including the basic MIPS instructions alu operations, ALU control implementation
To Search:
- [ddr_code] - FPGA-based DDR SDRAM controller VHDL har
- [VHDL1] - Learning to use FPGA to design a signal
File list (Check if you may need any files):
ALUC\.lso
....\alu.bgn
....\alu.bit
....\alu.bld
....\alu.drc
....\alu.ncd
....\alu.ngd
....\alu.pad
....\alu.par
....\alu.pcf
....\alu.ptwx
....\alu.twr
....\alu.twx
....\alu.unroutes
....\alu.ut
....\alu.v
....\alu.xpi
....\aluc.bgn
....\aluc.bit
....\aluc.bld
....\aluc.cmd_log
....\aluc.drc
....\ALUC.ise
....\aluc.lso
....\aluc.ncd
....\aluc.ngc
....\aluc.ngd
....\aluc.ngr
....\ALUC.ntrc_log
....\aluc.pad
....\aluc.par
....\aluc.pcf
....\aluc.prj
....\aluc.ptwx
....\ALUC.restore
....\aluc.stx
....\aluc.syr
....\aluc.twr
....\aluc.twx
....\aluc.unroutes
....\aluc.ut
....\aluc.v
....\aluc.xpi
....\aluc.xst
....\ALUctr.prj
....\ALUctr.stx
....\aluctr.v
....\ALUctr.xst
....\aluc_guide.ncd
....\aluc_isim_beh.wfs
....\aluc_map.map
....\aluc_map.mrp
....\aluc_map.ncd
....\aluc_map.ngm
....\aluc_map.xrpt
....\aluc_ngdbuild.xrpt
....\aluc_pad.csv
....\aluc_pad.txt
....\aluc_par.xrpt
....\aluc_prev_built.ngd
....\aluc_summary.html
....\aluc_summary.xml
....\aluc_ucf.ucf
....\aluc_usage.xml
....\ALUC_xdb\cst.xbcd
....\........\tmp\ise\version
....\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
....\........\...\...\............\..................\.........\HDProject_StrTbl
....\........\...\...\............\..................\__stored_object_table__
....\........\...\...\............\ISimPlugin\SignalOrdering1\aluc_isim_beh.exe
....\........\...\...\............\..........\...............\aluc_isim_beh.exe_StrTbl
....\........\...\...\............\..........\...............\Rtype_test_isim_beh.exe
....\........\...\...\............\..........\...............\Rtype_test_isim_beh.exe_StrTbl
....\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
....\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
....\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
....\........\...\...\............\................\................\dpm_project_main_StrTbl
....\........\...\...\............\................\................\NameMap
....\........\...\...\............\................\................\NameMap_StrTbl
....\........\...\...\............\................\__stored_objects__
....\........\...\...\............\................\__stored_objects___StrTbl
....\........\...\...\............\................\__stored_object_table__
....\........\...\...\............\................Gui\GuiProjectData
....\........\...\...\............\...................\GuiProjectData_StrTbl
....\........\...\...\............\xreport\Gc_RvReportViewer-Current-Module
....\........\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-aluc
....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-aluc_StrTbl
....\........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
....\........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
....\........\...\...\..REGISTRY__\Autonym\regkeys
....\........\...\...\............\bitgen\regkeys
....\........\...\...\............\common\regkeys
....\........\...\...\............\.pldfit\regkeys
....\........\...\...\............\Cs\regkeys
....\........\...\...\............\dumpngdio\regkeys
....\........\...\...\............\fuse\regkeys
....\........\...\...\............\HierarchicalDesign\HDProject\regkeys
....\........\...\...\............\..................\regkeys
....\........\...\...\............\hprep6\regkeys
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