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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 1kb
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- Author ：林****
- About ： Nobody
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1:1 duty cycle of the divider of the VHDL implementation, including the odd and even frequency.
Packet file list
(Preview for download)
frediv\fredivn.vhd
......\fredivn1.vhd
frediv
......\fredivn1.vhd
frediv
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