I use the VGA controller to write Verilog code.

My_VGA\db\logic_util_heursitic.dat
......\..\prev_cmp_vga.asm.qmsg
......\..\prev_cmp_vga.eda.qmsg
......\..\prev_cmp_vga.fit.qmsg
......\..\prev_cmp_vga.map.qmsg
......\..\prev_cmp_vga.qmsg
......\..\prev_cmp_vga.tan.qmsg
......\..\vga.asm.qmsg
......\..\vga.asm.rdb
......\..\vga.asm_labs.ddb
......\..\vga.cbx.xml
......\..\vga.cmp.cdb
......\..\vga.cmp.hdb
......\..\vga.cmp.kpt
......\..\vga.cmp.logdb
......\..\vga.cmp.rdb
......\..\vga.cmp.tdb
......\..\vga.cmp0.ddb
......\..\vga.db_info
......\..\vga.eco.cdb
......\..\vga.eda.qmsg
......\..\vga.fit.qmsg
......\..\vga.hier_info
......\..\vga.hif
......\..\vga.lpc.html
......\..\vga.lpc.rdb
......\..\vga.lpc.txt
......\..\vga.map.cdb
......\..\vga.map.hdb
......\..\vga.map.logdb
......\..\vga.map.qmsg
......\..\vga.pre_map.cdb
......\..\vga.pre_map.hdb
......\..\vga.rtlv.hdb
......\..\vga.rtlv_sg.cdb
......\..\vga.rtlv_sg_swap.cdb
......\..\vga.sgdiff.cdb
......\..\vga.sgdiff.hdb
......\..\vga.sld_design_entry.sci
......\..\vga.sld_design_entry_dsc.sci
......\..\vga.smart_action.txt
......\..\vga.syn_hier_info
......\..\vga.tan.qmsg
......\..\vga.tis_db_list.ddb
......\..\vga.tmw_info
......\incremental_db\compiled_partitions\vga.root_partition.map.kpt
......\..............\README
......\simulation\modelsim\vga.sft
......\..........\........\vga.vo
......\..........\........\vga_modelsim.xrf
......\..........\........\vga_v.sdo
......\vga.asm.rpt
......\vga.cdf
......\vga.done
......\vga.dpf
......\vga.eda.rpt
......\vga.fit.rpt
......\vga.fit.summary
......\vga.flow.rpt
......\vga.map.rpt
......\vga.map.summary
......\vga.pin
......\vga.pof
......\vga.qpf
......\vga.qsf
......\vga.qws
......\vga.tan.rpt
......\vga.tan.summary
......\vga.v
......\vga.v.bak
......\incremental_db\compiled_partitions
......\simulation\modelsim
......\db
......\incremental_db
......\simulation
My_VGA

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