Description: eee.std_logic_arith.all
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity PL_auto1 is
port ( clk:in std_logic --系统时钟
set,get,sel,finish: in std_logic --设定、买、选择、完成信号
coin0,coin1: in std_logic --5角硬币、1元硬币
price,quantity :in std_logic_vector(3 downto 0) --价格、数量数据
item0 , act:out std_l
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实验五 数字钟.doc
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