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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 3kb
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- Author ：m****
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Introduction - If you have any usage issues, please Google them yourself
This module is to use asynchronous clock synchronization input signal, the signal for the state machine, decreases the probability of runaway."
Packet file list
(Preview for download)
sync_neg.v
PCI9054_485.flow.rpt
PCI9054_485.flow.rpt
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