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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 2kb
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- Author ：jing****
- About ： Nobody
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Introduction - If you have any usage issues, please Google them yourself
In the Xilinx development board implements two led digital tube from 0 to 99 seconds to count by experiment.
Packet file list
(Preview for download)
led.v
led_test.v
segled.ucf
led_test.v
segled.ucf
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