State machines with FPGA implementation process, with VrilogHDL achieve, we want to help

state_machine1
..............\download
..............\........\state_machine.bit
..............\........\state_machine.mcs
..............\........\state_machine.ucf
..............\project
..............\.......\automake.log
..............\.......\bitgen.ut
..............\.......\compxlib.cfg
..............\.......\compxlib.log
..............\.......\compxlib.log.bak
..............\.......\modelsim.ini
..............\.......\project.cxl
..............\.......\project.dhp
..............\.......\project.ise
..............\.......\project.ise_ISE_Backup
..............\.......\state_machine.bgn
..............\.......\state_machine.bit
..............\.......\state_machine.bld
..............\.......\state_machine.cmd_log
..............\.......\state_machine.drc
..............\.......\state_machine.lfp
..............\.......\state_machine.lso
..............\.......\state_machine.mrp
..............\.......\state_machine.nc1
..............\.......\state_machine.ncd
..............\.......\state_machine.ngc
..............\.......\state_machine.ngd
..............\.......\state_machine.ngm
..............\.......\state_machine.ngr
..............\.......\state_machine.pad
..............\.......\state_machine.pad_txt
..............\.......\state_machine.par
..............\.......\state_machine.pcf
..............\.......\state_machine.placed_ncd_tracker
..............\.......\state_machine.prj
..............\.......\state_machine.routed_ncd_tracker
..............\.......\state_machine.stx
..............\.......\state_machine.syr
..............\.......\state_machine.twr
..............\.......\state_machine.twx
..............\.......\state_machine.ucf
..............\.......\state_machine.ucf.untf
..............\.......\state_machine.ut
..............\.......\state_machine.v
..............\.......\state_machine.xpi
..............\.......\state_machine_last_par.ncd
..............\.......\state_machine_map.ncd
..............\.......\state_machine_map.ngm
..............\.......\state_machine_pad.csv
..............\.......\state_machine_pad.txt
..............\.......\state_machine_summary.html
..............\.......\state_machine_vhdl.prj
..............\.......\xst
..............\.......\...\dump.xst
..............\.......\...\........\state_machine.prj
..............\.......\...\........\.................\ngx
..............\.......\...\........\.................\...\notopt
..............\.......\...\........\.................\...\opt
..............\.......\...\work
..............\.......\...\....\hdllib.ref
..............\.......\...\....\vlg4D
..............\.......\...\....\.....\state__machine.bin
..............\.......\_impact.cmd
..............\.......\_impact.log
..............\.......\_ngo
..............\.......\....\netlist.lst
..............\.......\_pace.ucf
..............\.......\_xmsgs
..............\.......\__projnav
..............\.......\__projnav.log
..............\.......\.........\bitgen.rsp
..............\.......\.........\ednTOngd_tcl.rsp
..............\.......\.........\nc1TOncd_tcl.rsp
..............\.......\.........\parentAssignPackagePinsApp_tcl.rsp
..............\.......\.........\project.gfl
..............\.......\.........\project_flowplus.gfl
..............\.......\.........\runXst_tcl.rsp
..............\.......\.........\state_machine.xst
..............\.......\.........\state_machine_ncdTOut_tcl.rsp
..............\.......\.........\sumrpt_tcl.rsp
..............\rtl
..............\...\state_machine.v

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