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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 5.67mb
  • Downloaded :0次
  • Author :cha***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
this code is Universal Asynchronous Transreciver this project is IEEE 2008 standard this project is done by my personal and i had verilog code.
Packet file list
(Preview for download)
rk\.lso
..\aaaa.ant
..\aaaa.jhd
..\aaaa.tbw
..\aaaa.vhw
..\aaaa.xwv
..\aaaa.xwv_bak
..\aaaa_beh.prj
..\aaaa_bencher.prj
..\aaaa_isim_beh.exe
..\aaaa_isim_beh.wfs
..\andgate.vhd
..\asdf.ant
..\asdf.jhd
..\asdf.tbw
..\asdf.xwv
..\asdf.xwv_bak
..\asdf_beh.prj
..\asdf_bencher.prj
..\asdf_isim_beh.exe
..\asdf_isim_beh.wfs
..\asf.ant
..\asf.jhd
..\asf.tbw
..\asf.xwv
..\asf.xwv_bak
..\asff.ant
..\asff.jhd
..\asff.tbw
..\asff.xwv
..\asff.xwv_bak
..\asff_beh.prj
..\asff_bencher.prj
..\asff_isim_beh.exe
..\asff_isim_beh.wfs
..\asfifo.cmd_log
..\asfifo.lso
..\asfifo.ngc
..\asfifo.ngr
..\asfifo.prj
..\asfifo.stx
..\asfifo.syr
..\asfifo.vhd
..\asfifo.xst
..\asfifo1.vhd
..\asfifo_bencher.prj
..\asfifo_summary.html
..\asfifo_vhdl.prj
..\asf_beh.prj
..\asf_bencher.prj
..\asf_isim_beh.exe
..\asf_isim_beh.wfs
..\baudra.ant
..\baudra.jhd
..\baudra.tbw
..\baudra.xwv
..\baudra.xwv_bak
..\baudrate.cmd_log
..\baudrate.lso
..\baudrate.ngc
..\baudrate.ngr
..\baudrate.prj
..\baudrate.stx
..\baudrate.syr
..\baudrate.vhd
..\baudrate.xst
..\baudratea.vhd
..\baudrateb.vhd
..\baudratec.vhd
..\baudrate_summary.html
..\baudrate_vhdl.prj
..\baudra_beh.prj
..\baudra_bencher.prj
..\baudra_isim_beh.exe
..\baudra_isim_beh.wfs
..\baudtbw.xwv
..\baudtbw.xwv_bak
..\baudtbw_bencher.prj
..\br.ant
..\br.jhd
..\br.tbw
..\br.xwv
..\br.xwv_bak
..\br_beh.prj
..\br_isim_beh.exe
..\br_isim_beh.wfs
..\bsai.ant
..\bsai.jhd
..\bsai.tbw
..\bsai.xwv
..\bsai.xwv_bak
..\bsaid.ant
..\bsaid.jhd
..\bsaid.tbw
..\bsaid.xwv
..\bsaid.xwv_bak
..\bsaid_beh.prj
..\bsaid_isim_beh.exe
..\bsaid_isim_beh.wfs
..\bsai_beh.prj
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