about and gate user with verilog hdl

AND2V1\smartgen\smartgen.aws
......\hdl\AND2V1.v
......\viewdraw\viewdraw.ini
......\........\.f\project.lst
......\simulation\run.do
......\..........\modelsim.log
......\..........\postsynth\_info
......\..........\.........\_vmake
......\..........\.........\@a@n@d2@v1\_primary.vhd
......\..........\.........\..........\verilog.psm
......\..........\.........\..........\verilog.prw
......\..........\.........\..........\_primary.dbs
......\..........\.........\..........\_primary.dat
......\..........\.........\stimulus\_primary.vhd
......\..........\.........\........\verilog.psm
......\..........\.........\........\verilog.prw
......\..........\.........\........\_primary.dbs
......\..........\.........\........\_primary.dat
......\..........\.........\testbench\_primary.vhd
......\..........\.........\.........\verilog.psm
......\..........\.........\.........\verilog.prw
......\..........\.........\.........\_primary.dbs
......\..........\.........\.........\_primary.dat
......\..........\.........\and21\_primary.vhd
......\..........\.........\.....\verilog.psm
......\..........\.........\.....\verilog.prw
......\..........\.........\.....\_primary.dbs
......\..........\.........\.....\_primary.dat
......\..........\.........\tb_clock_minmax\_primary.vhd
......\..........\.........\...............\verilog.psm
......\..........\.........\...............\verilog.prw
......\..........\.........\...............\_primary.dbs
......\..........\.........\...............\_primary.dat
......\..........\vsim.wlf
......\..........\modelsim.ini
......\.ynthesis\stdout.log
......\.........\.yntmp\AND2V1_flink.htm
......\.........\......\AND2V1_srr.htm
......\.........\......\AND2V1_toc.htm
......\.........\......\sap.log
......\.........\......\AND2V1.plg
......\.........\......\sap_log_flink.htm
......\.........\......\sap_log_srr.htm
......\.........\......\AND2V1.msg
......\.........\......\and21_flink.htm
......\.........\......\and21_srr.htm
......\.........\......\and21_toc.htm
......\.........\......\and21.plg
......\.........\......\and21.msg
......\.........\backup\AND2V1.srr
......\.........\......\and21.srr
......\.........\run_options.txt
......\.........\scratchproject.prs
......\.........\AND2V1.tlg
......\.........\AND2V1.srl
......\.........\AND2V1.htm
......\.........\AND2V1.sap
......\.........\AND2V1.fse
......\.........\AND2V1.szr
......\.........\AND2V1.srd
......\.........\AND2V1.srm
......\.........\AND2V1.map
......\.........\AND2V1.edn
......\.........\AND2V1.sdf
......\.........\AND2V1.pdc
......\.........\AND2V1_sdc.sdc
......\.........\AND2V1.so
......\.........\AND2V1.areasrr
......\.........\AND2V1.v
......\.........\AND2V1_syn.prj
......\.........\AND2V1.srr
......\.........\AND2V1.srs
......\.........\and21.tlg
......\.........\and21.srl
......\.........\and21.htm
......\.........\and21.sap
......\.........\and21.fse
......\.........\and21.szr
......\.........\and21.srd
......\.........\and21.srm
......\.........\and21.map
......\.........\and21.edn
......\.........\and21.sdf
......\.........\and21.pdc
......\.........\and21_sdc.sdc
......\.........\and21.so
......\.........\and21.areasrr
......\.........\and21.v
......\.........\and21_syn.prd
......\.........\and21_syn.prj
......\.........\and21.srr
......\.........\identify.log
......\.........\and21.srs
......\.timulus\AND2V1.hpj
......\........\waveperl.log
......\........\BtimErrors.log
......\........\files_to_build.txt
......\........\AND2V1_tbench.btim
......\........\AND2V1_tbench.v
......\........\AND2V1.dsk

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