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create_pulse

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 542kb
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  • Author :王***
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Introduction - If you have any usage issues, please Google them yourself
create the fre with verilog hdl
Packet file list
(Preview for download)
create_pulse\smartgen\smartgen.aws
............\hdl\create_pulse.vhd
............\...\pulse.vhd
............\...\addspeed.vhd
............\...\reset.vhd
............\...\fre_12_div.vhd
............\viewdraw\vf\project.lst
............\........\sym\create_pulse.1
............\........\viewdraw.ini
............\simulation\run.do
............\..........\modelsim.log
............\..........\postsynth\_info
............\..........\.........\_vmake
............\..........\.........\fre_12_div\_primary.dbs
............\..........\.........\..........\_primary.dat
............\..........\.........\..........\def_arch.dbs
............\..........\.........\..........\def_arch.dat
............\..........\.........\..........\def_arch.psm
............\..........\.........\..........\def_arch.prw
............\..........\.........\reset\_primary.dbs
............\..........\.........\.....\_primary.dat
............\..........\.........\.....\def_arch.dbs
............\..........\.........\.....\def_arch.dat
............\..........\.........\.....\def_arch.psm
............\..........\.........\.....\def_arch.prw
............\..........\.........\create_pulse\_primary.dbs
............\..........\.........\............\_primary.dat
............\..........\.........\............\def_arch.dbs
............\..........\.........\............\def_arch.dat
............\..........\.........\............\def_arch.psm
............\..........\.........\............\def_arch.prw
............\..........\.........\stimulus\_primary.dbs
............\..........\.........\........\_primary.dat
............\..........\.........\........\stimulator.dbs
............\..........\.........\........\stimulator.dat
............\..........\.........\........\stimulator.psm
............\..........\.........\........\stimulator.prw
............\..........\.........\testbench\_primary.dbs
............\..........\.........\.........\_primary.dat
............\..........\.........\.........\tbgeneratedcode.dbs
............\..........\.........\.........\tbgeneratedcode.dat
............\..........\.........\.........\tbgeneratedcode.psm
............\..........\.........\.........\tbgeneratedcode.prw
............\..........\tb.log
............\..........\vsim.wlf
............\..........\wave.do
............\..........\modelsim.ini.sav
............\..........\modelsim.ini
............\.ynthesis\identify.log
............\.........\stdout.log
............\.........\.yntmp\delay_flink.htm
............\.........\......\delay_srr.htm
............\.........\......\delay_toc.htm
............\.........\......\sap.log
............\.........\......\delay.plg
............\.........\......\sap_log_flink.htm
............\.........\......\sap_log_srr.htm
............\.........\......\delay.msg
............\.........\......\delay_1_flink.htm
............\.........\......\delay_1_srr.htm
............\.........\......\delay_1_toc.htm
............\.........\......\delay_1.msg
............\.........\......\create_pulse_flink.htm
............\.........\......\create_pulse_srr.htm
............\.........\......\create_pulse_toc.htm
............\.........\......\create_pulse.plg
............\.........\......\create_pulse.msg
............\.........\backup\delay.srr
............\.........\......\create_pulse.srr
............\.........\run_options.txt
............\.........\scratchproject.prs
............\.........\create_pulse.srs
............\.........\delay.tlg
............\.........\.recordref
............\.........\delay.srs
............\.........\delay.srl
............\.........\delay.htm
............\.........\delay.sap
............\.........\delay.fse
............\.........\create_pulse.srr
............\.........\delay.szr
............\.........\create_pulse_syn.prj
............\.........\delay.srd
............\.........\delay.srm
............\.........\delay.map
............\.........\delay.edn
............\.........\delay.sdf
............\.........\delay.pdc
............\.........\delay_sdc.sdc
............\.........\delay.so
............\.........\delay.areasrr
............\.........\dela
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