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DSD_assignment

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 946kb
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  • Author :史****
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(Preview for download)
5080369079_史婕茹_DSD作业_2011_05_23
....................................\5080369079_史婕茹_DSD作业_2011_05_23.pdf
....................................\homework1
....................................\homework10
....................................\..........\lab10.cr.mti
....................................\..........\lab10.mpf
....................................\..........\shift_register_4b.v
....................................\..........\shift_register_4b.v.bak
....................................\..........\tb_shift_register4b.v
....................................\..........\tb_shift_register4b.v.bak
....................................\..........\vsim.wlf
....................................\..........\work
....................................\..........\....\shift_register_4b
....................................\..........\....\.................\verilog.asm
....................................\..........\....\.................\_primary.dat
....................................\..........\....\.................\_primary.vhd
....................................\..........\....\tb_shift_register4b
....................................\..........\....\...................\verilog.asm
....................................\..........\....\...................\_primary.dat
....................................\..........\....\...................\_primary.vhd
....................................\..........\....\_info
....................................\..........\....\_temp
....................................\homework11
....................................\..........\freq_div3.v
....................................\..........\freq_div3.v.bak
....................................\..........\lab11.cr.mti
....................................\..........\lab11.mpf
....................................\..........\tb_freq_div3.v
....................................\..........\tb_freq_div3.v.bak
....................................\..........\vsim.wlf
....................................\..........\work
....................................\..........\....\freq_div_3
....................................\..........\....\..........\verilog.asm
....................................\..........\....\..........\_primary.dat
....................................\..........\....\..........\_primary.vhd
....................................\..........\....\tb_freq_div3
....................................\..........\....\............\verilog.asm
....................................\..........\....\............\_primary.dat
....................................\..........\....\............\_primary.vhd
....................................\..........\....\_info
....................................\..........\....\_temp
....................................\homework12
....................................\..........\counter8b_updown.v
....................................\..........\counter8b_updown.v.bak
....................................\..........\lab12.cr.mti
....................................\..........\lab12.mpf
....................................\..........\tb_counter8b_updown.v
....................................\..........\tb_counter8b_updown.v.bak
....................................\..........\vsim.wlf
....................................\..........\work
....................................\..........\....\counter8b_updown
....................................\..........\....\................\verilog.asm
....................................\..........\....\................\_primary.dat
....................................\..........\....\................\_primary.vhd
....................................\..........\....\tb_counter8b_updown
....................................\..........\....\...................\verilog.asm
....................................\..........\....\...................\_primary.dat
....................................\..........\....\...................\_primary.vhd
....................................\..........\....\_info
....................................\..........\....\_temp
.................................
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