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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 2.3mb
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- Author ：刘***
- About ： Nobody
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Introduction - If you have any usage issues, please Google them yourself
Asynchronous FIFO is the electric circuit which one kind advanced leaves first, uses when needs to produce data interface s part, uses for to save, the cushion between two asynchronous clock s data transmissions.
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(Preview for download)
异步FIFO结构及FPGA设计.doc
fifo_generator_ds317.pdf
fifo_generator_ug175.pdf
fifo_generator_ds317.pdf
fifo_generator_ug175.pdf
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