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smg_interface

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 53kb
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  • Author :shi****
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Introduction - If you have any usage issues, please Google them yourself
FIFO high-speed data acquisition and processing, sending and receiving serial package, independent of the previous module,
Packet file list
(Preview for download)
smg_interface\smg_control_module\number_control_module.v.bak
.............\..................\smg_control_module.v
.............\..................\smg_control_module.v.bak
.............\..................\transcript
.............\....encode_module\smg_encode_module.v
.............\.................\smg_encode_module.v.bak
.............\smg_interface.asm.rpt
.............\smg_interface.done
.............\smg_interface.fit.rpt
.............\smg_interface.fit.summary
.............\smg_interface.flow.rpt
.............\smg_interface.map.rpt
.............\smg_interface.map.summary
.............\smg_interface.pin
.............\smg_interface.pof
.............\smg_interface.qpf
.............\smg_interface.qsf
.............\smg_interface.sof
.............\smg_interface.tan.rpt
.............\smg_interface.tan.summary
.............\smg_interface.v
.............\smg_interface.v.bak
.............\smg_interface_assignment_defaults.qdf
.............\....scan_module\smg_scan_module.v
.............\...............\smg_scan_module.v.bak
.............\db
.............\incremental_db
.............\smg_control_module
.............\smg_encode_module
.............\smg_scan_module
smg_interface
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