Operation of this project is to introduce an I2C bus interface EEPROM AT24C08 approach, allowing users to understand the I2C bus protocol read and write methods. 2, through the JTAG port to I2C_FPGA.sof downloaded to the FPGA, the first long press the reset button about 1 seconds to initialize. Click the experimental board KEY1 key counter by one calculation, and the results written to EEPROM, and also showed the lowest level in the digital control, according to data from the EEPROM KEY0 read out and displayed on the digital control.

I2C_v
.....\at24c08.pdf
.....\delay_reset_block.bdf
.....\delay_reset_block.bsf
.....\i2c.bsf
.....\i2c.v
.....\i2c.v.bak
.....\I2C_AV_Config.bsf
.....\I2C_AV_Config.v
.....\I2C_AV_Config.v.bak
.....\I2C_Controller.bsf
.....\I2C_Controller.v
.....\I2C_Controller.v.bak
.....\I2C_FPGA.asm.rpt
.....\I2C_FPGA.bdf
.....\I2C_FPGA.cdf
.....\I2C_FPGA.done
.....\I2C_FPGA.dpf
.....\I2C_FPGA.fit.eqn
.....\I2C_FPGA.fit.rpt
.....\I2C_FPGA.fit.smsg
.....\I2C_FPGA.fit.summary
.....\I2C_FPGA.flow.rpt
.....\I2C_FPGA.map.eqn
.....\I2C_FPGA.map.rpt
.....\I2C_FPGA.map.summary
.....\I2C_FPGA.pin
.....\I2C_FPGA.pof
.....\I2C_FPGA.qpf
.....\I2C_FPGA.qsf
.....\I2C_FPGA.qws
.....\I2C_FPGA.sof
.....\I2C_FPGA.tan.rpt
.....\I2C_FPGA.tan.summary
.....\I2C_FPGA_assignment_defaults.qdf
.....\i2c_test.bsf
.....\i2c_test.v
.....\i2c_test.v.bak
.....\i2c总线协议.pdf
.....\reset_counter.bsf
.....\reset_counter.v
.....\reset_counter_bb.v
.....\setup.tcl
.....\setup.tcl.bak

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