100 POWER TIPS FOR DESIGN FPGA

src_book
........\13.14.15.coding
........\...............\rtl
........\...............\...\coding_style.v
........\...............\...\simple.v
........\...............\...\synth_support.v
........\...............\...\tb.v
........\...............\synth
........\...............\.....\isim.cmd
........\...............\.....\sim1.wcfg
........\...............\.....\sim2.wcfg
........\...............\.....\synth.xise
........\...............\.....\synth_support.lso
........\16.inference
........\............\rtl
........\............\...\inference.v
........\............\synth
........\............\.....\inference.lso
........\............\.....\inference.ptwx
........\............\.....\inference.stx
........\............\.....\inference.unroutes
........\............\.....\inference.xpi
........\............\.....\inference_map.mrp
........\............\.....\netgen
........\............\.....\......\map
........\............\.....\......\...\inference_map.sdf
........\............\.....\......\...\inference_map.v
........\............\.....\......\synthesis
........\............\.....\......\.........\inference_synthesis.v
........\............\.....\synth.xise
........\17.mixed_verilog_vhdl
........\.....................\rtl
........\.....................\...\counter.vhd
........\.....................\...\tb.v
........\.....................\...\top.v
........\.....................\synth
........\.....................\.....\isim.cmd
........\.....................\.....\synth.xise
........\.....................\.....\top.lso
........\.....................\.....\top.ptwx
........\.....................\.....\top.stx
........\.....................\.....\top_map.mrp
........\18.verilog
........\..........\rtl
........\..........\...\verilog2001.v
........\..........\synth
........\..........\.....\synth.xise
........\..........\.....\verilog2001.lso
........\..........\.....\verilog2001.stx
........\..........\.....\verilog2001_map.mrp
........\20.21.clocking
........\..............\cores
........\..............\.....\.lso
........\..............\.....\blk_mem.v
........\..............\.....\blk_mem.xco
........\..............\.....\clka_mmcm.v
........\..............\.....\clka_mmcm.xco
........\..............\.....\clk_dcm.v
........\..............\.....\clk_dcm.xco
........\..............\.....\clk_mmcm.v
........\..............\.....\clk_mmcm.xco
........\..............\.....\coregen.cgp
........\..............\rtl
........\..............\...\clock_dcm.v
........\..............\...\clock_inference.v
........\..............\...\clock_mmcm.v
........\..............\...\clock_schemes.v
........\..............\...\timing_analyzer.v
........\..............\synth
........\..............\.....\clock_dcm.lso
........\..............\.....\clock_dcm.ptwx
........\..............\.....\clock_dcm.stx
........\..............\.....\clock_dcm.ucf
........\..............\.....\clock_dcm.unroutes
........\..............\.....\clock_dcm.xpi
........\..............\.....\clock_dcm_map.mrp
........\..............\.....\clock_inference.ptwx
........\..............\.....\clock_inference.ucf
........\..............\.....\clock_inference.unroutes
........\..............\.....\clock_inference.xpi
........\..............\.....\clock_inference_map.mrp
........\..............\.....\clock_mmcm.clk_rgn
........\..............\.....\clock_mmcm.dly
........\..............\.....\clock_mmcm.lso
........\..............\.....\clock_mmcm.ptwx
........\..............\.....\clock_mmcm.pwr
........\..............\.....\clock_mmcm.stx
........\..............\.....\clock_mmcm.unroutes
........\..............\.....\clock_mmcm.xpi
........\..............\.....\clock_mmcm_map.mrp
........\..............\.....\netgen
........\..............\.....\......\par
........\..............\.....\......\...\clock_mmcm_timesim.sdf
........\..............\.....\......\...\clock_mmcm_timesim.v
........\..............\.....\planAhead_run_1
........\..............\.....\...............\synth.data
........\..............\.....\...............\..........\constrs_1
........\..........

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