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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 1kb
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- Author ：safe****
- About ： Nobody
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Introduction - If you have any usage issues, please Google them yourself
A FSM that extracts the 18 LSB out of a 128 bit vector and forwards it as a 18 bit vector.
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(Preview for download)
downsizer.vhd
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