An ALU project in VHDL work perfectly

transcript
vsim.wlf
_info
~$Lab1.docx
ADD_N.vhd
ADD_N.vhd.bak
ADD_N_TEST.vhd
ADD_N_TEST.vhd.bak
ADD_try.vhd
AND_N.vhd
AND_N.vhd.bak
AND_N_TEST.vhd
AND_N_TEST.vhd.bak
ARITH_PACK.vhd
ARITH_PACK.vhd.bak
ARITH_UNIT.vhd
ARITH_UNIT_TEST.vhd
DIV_N.vhd
DIV_N.vhd.bak
DIV_N_TEST.vhd
DIV_N_TEST.vhd.bak
DIV_N_TESTbackup.vhd
DIV_Nbackup.vhd
Lab1.cr.mti
Lab1.mpf
Laboratory 1.pdf
LOGIC_PACK
LOGIC_PACK.vhd
LOGIC_PACK.vhd.bak
LOGIC_UNIT.vhd
LOGIC_UNIT_TEST.vhd
LOGIC_UNIT_TEST.vhd.bak
MUL_N.vhd
MUL_N.vhd.bak
MUL_N_TEST.vhd
MUL_N_TEST.vhd.bak
NOT_N.vhd
NOT_N.vhd.bak
NOT_N_TEST.vhd
NOT_N_TEST.vhd.bak
OR_N.vhd
OR_N_TEST.vhd
OR_N_TEST.vhd.bak
register_test.vhd
STATUS_FLAG.vhd
SUB_N.vhd
SUB_N.vhd.bak
SUB_N_TEST.vhd
SUB_N_TEST.vhd.bak

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