Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: shiyanwu Download
 Description: VHDL programming to a main road, a country road. Composed of a crossroads, requiring priority to ensuring the main road traffic. MR (red), MY (main yellow), MG (green), CR (Township red), CY (Township yellow), CG (Township Green) six traffic lights need to be controlled traffic lights green → red four seconds of yellow light intervals by red → green interval of time system MRCY, MRCG, MYCR, MGCR four states
 Downloaders recently: [More information of uploader 1013900343]
 To Search:
File list (Check if you may need any files):
实验五.docx
    

CodeBus www.codebus.net