The FPGA chip, the output of the CCD camera analog video signal acquisition, converted to 640* 480 resolution video data, and temporarily stored in the external SRAM or SDRAM

yuanEDA\xlcj.qpf
.......\xlcj.qsf
.......\db\xlcj2.hif
.......\..\xlcj.db_info
.......\..\xlcj1.fit.qmsg
.......\..\xlcj1.pre_map.hdb
.......\..\xlcj1.cmp.rdb
.......\..\xlcj1.signalprobe.cdb
.......\..\xlcj1.map.cdb
.......\..\xlcj1.sld_design_entry.sci
.......\..\xlcj1.asm.qmsg
.......\..\xlcj2.psp
.......\..\xlcj1.map.hdb
.......\..\xlcj1.cmp.ecobp
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.......\..\xlcj1.cmp_bb.logdb
.......\..\xlcj2.dbp
.......\..\xlcj1.cmp_bb.rcf
.......\..\xlcj1.eda.qmsg
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.......\..\jsq.db_info
.......\..\xlcj1.tan.qmsg
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.......\..\xlcj1.map.bpm
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.......\..\xlcj1.eco.cdb
.......\..\xlcj1.sgdiff.cdb
.......\..\xlcj1.sgdiff.hdb
.......\..\xlcj1.map_bb.cdb
.......\..\xlcj1.rtlv_sg.cdb
.......\..\wed.wsf
.......\..\xlcj1.rtlv.hdb
.......\..\xlcj1.merge.qmsg
.......\..\xlcj1.sld_design_entry_dsc.sci
.......\..\xlcj1.cmp.cdb
.......\..\xlcj3.hif
.......\..\jsq.cbx.xml
.......\..\jsq.hif
.......\..\jsq.hier_info
.......\..\jsq.rtlv_sg.cdb
.......\..\xlcj1.map_bb.hdb
.......\..\jsq.rtlv.hdb
.......\..\jsq.rtlv_sg_swap.cdb
.......\..\jsq.pre_map.hdb
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.......\..\jsq.psp
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.......\..\xlcj3.pss
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.......\..\xlcj2.sgdiff.cdb
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.......\..\xlcj2.signalprobe.cdb
.......\..\xlcj2.rtlv_sg.cdb
.......\..\xlcj2.rtlv.hdb
.......\..\xlcj2.rtlv_sg_swap.cdb
.......\..\xlcj2.pre_map.hdb
.......\..\block1.dbp
.......\..\xlcj2.syn_hier_info
.......\..\xlcj2.cmp.rdb
.......\..\block1.pss
.......\..\jsq.cmp.bpm
.......\..\jsq.cmp.ecobp
.......\..\jsq.cmp_bb.logdb
.......\..\jsq.cmp_bb.rcf
.......\..\jsq.cmp_bb.cdb
.......\..\xlcj2.map_bb.hdb

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