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LogicLock

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 80kb
  • Downloaded :0次
  • Author :myn***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Comes through the Quartus software engineering examples- " lockmult" to become familiar with Altera Quartus II logic lock LogicLock to use.
Packet file list
(Preview for download)
LogicLock\logiclock\lockmult\cmp_state.ini
.........\.........\........\lockmult.qpf
.........\.........\........\lockmult.qws
.........\.........\........\mult.v
.........\.........\........\pipemult.asm.rpt
.........\.........\........\pipemult.bdf
.........\.........\........\pipemult.done
.........\.........\........\pipemult.fit.eqn
.........\.........\........\pipemult.fit.rpt
.........\.........\........\pipemult.fit.summary
.........\.........\........\pipemult.flow.rpt
.........\.........\........\pipemult.map.eqn
.........\.........\........\pipemult.map.rpt
.........\.........\........\pipemult.map.summary
.........\.........\........\pipemult.pin
.........\.........\........\pipemult.pof
.........\.........\........\pipemult.qsf
.........\.........\........\pipemult.sof
.........\.........\........\pipemult.tan.rpt
.........\.........\........\pipemult.tan.summary
.........\.........\........\pipemult_assignment_defaults.qdf
.........\.........\........\ram.v
.........\.........\topmult\cmp_state.ini
.........\.........\.......\mult.v
.........\.........\.......\pipemult.bdf
.........\.........\.......\ram.v
.........\.........\.......\topmult.bdf
.........\.........\.......\topmult.qpf
.........\.........\.......\topmult.qsf
.........\.........\.......\topmult.qws
.........\.........\.......\topmult_assignment_defaults.qdf
.........\.........\lockmult
.........\.........\topmult
.........\logiclock
LogicLock
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