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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 219kb
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  • Author :阿***
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Digital electronic circuits in the D trigger VHDL realization
Packet file list
(Preview for download)
shiyan\proj1.qpf
......\proj1.qsf
......\db\wed.wsf
......\..\proj1.db_info
......\..\proj1.asm.qmsg
......\..\proj1.asm_labs.ddb
......\..\proj1.cmp.rdb
......\..\proj1.tan.qmsg
......\..\prev_cmp_proj1.qmsg
......\..\proj1.cmp.tdb
......\..\proj1.cmp.hdb
......\..\proj1.sim.qmsg
......\..\proj1.cbx.xml
......\..\proj1.cmp0.ddb
......\..\proj1.eco.cdb
......\..\proj1.cmp.cdb
......\..\proj1.sim_ori.vwf
......\..\proj1.sim.hdb
......\..\proj1.eds_overflow
......\..\prev_cmp_proj1.map.qmsg
......\..\proj1.sim.rdb
......\..\prev_cmp_proj1.fit.qmsg
......\..\prev_cmp_proj1.asm.qmsg
......\..\prev_cmp_proj1.tan.qmsg
......\..\proj1.rpp.qmsg
......\..\proj1.sld_design_entry.sci
......\..\proj1.sgate.rvd
......\..\proj1.sgate_sm.rvd
......\..\prev_cmp_proj1.sim.qmsg
......\..\proj1.hif
......\..\proj1.map.qmsg
......\..\proj1.hier_info
......\..\proj1.rtlv_sg.cdb
......\..\proj1.rtlv.hdb
......\..\proj1.rtlv_sg_swap.cdb
......\..\proj1.lpc.txt
......\..\proj1.lpc.html
......\..\proj1.lpc.rdb
......\..\proj1.pre_map.hdb
......\..\proj1.pre_map.cdb
......\..\proj1.map_bb.logdb
......\..\proj1.sgdiff.cdb
......\..\proj1.sgdiff.hdb
......\..\proj1.sld_design_entry_dsc.sci
......\..\proj1.syn_hier_info
......\..\proj1.map_bb.cdb
......\..\proj1.map_bb.hdb
......\..\proj1.map.ecobp
......\..\proj1.map.kpt
......\..\proj1.cmp_merge.kpt
......\..\proj1.map.cdb
......\..\proj1.map.hdb
......\..\proj1.map.logdb
......\..\proj1.map.bpm
......\..\proj1.fit.qmsg
......\..\proj1.cmp.logdb
......\..\proj1_global_asgn_op.abo
......\..\proj1.cmp.kpt
......\..\proj1.cmp2.ddb
......\..\proj1.cmp.bpm
......\..\proj1.cmp.ecobp
......\..\proj1.tis_db_list.ddb
......\proj1.map.summary
......\incremental_db\compiled_partitions\proj1.root_partition.map.dpi
......\..............\...................\proj1.root_partition.map.kpt
......\..............\...................\proj1.root_partition.map.atm
......\..............\...................\proj1.root_partition.map.hdbx
......\..............\...................\proj1.root_partition.cmp.rcf
......\..............\...................\proj1.root_partition.cmp.hdbx
......\..............\...................\proj1.root_partition.cmp.atm
......\..............\...................\proj1.root_partition.cmp.logdb
......\..............\...................\proj1.root_partition.cmp.dfp
......\..............\...................\proj1.root_partition.cmp.kpt
......\..............\README
......\proj1.vhd.bak
......\proj1.vhd
......\proj1.map.rpt
......\proj1.pin
......\proj1.fit.smsg
......\proj1.fit.summary
......\proj1.fit.rpt
......\proj1.sof
......\proj1.pof
......\proj1.asm.rpt
......\proj1.tan.summary
......\proj1.tan.rpt
......\proj1.flow.rpt
......\proj1.done
......\proj1.dpf
......\proj1.vwf
......\proj1.sim.rpt
......\proj1.qws
......\incremental_db\compiled_partitions
......\db
......\incremental_db
shiyan
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