This procedure is based on the D flip-flop circuit connection diagram for the proof and the blocking assignments and nonblocking assignments to learn the difference between the simulation has been successful.

D
.\D.asm.rpt
.\D.bdf
.\D.done
.\D.fit.rpt
.\D.fit.smsg
.\D.fit.summary
.\D.flow.rpt
.\D.map.rpt
.\D.map.summary
.\D.pin
.\D.pof
.\D.qpf
.\D.qsf
.\D.qws
.\D.sim.rpt
.\D.sof
.\D.tan.rpt
.\D.tan.summary
.\D.vwf
.\db
.\..\D.asm.qmsg
.\..\D.asm_labs.ddb
.\..\D.cbx.xml
.\..\D.cmp.bpm
.\..\D.cmp.cdb
.\..\D.cmp.ecobp
.\..\D.cmp.hdb
.\..\D.cmp.logdb
.\..\D.cmp.rdb
.\..\D.cmp.tdb
.\..\D.cmp0.ddb
.\..\D.db_info
.\..\D.eco.cdb
.\..\D.eds_overflow
.\..\D.fit.qmsg
.\..\D.fnsim.cdb
.\..\D.fnsim.hdb
.\..\D.fnsim.qmsg
.\..\D.hier_info
.\..\D.hif
.\..\D.map.bpm
.\..\D.map.cdb
.\..\D.map.ecobp
.\..\D.map.hdb
.\..\D.map.logdb
.\..\D.map.qmsg
.\..\D.map_bb.cdb
.\..\D.map_bb.hdb
.\..\D.map_bb.hdbx
.\..\D.map_bb.logdb
.\..\D.pre_map.cdb
.\..\D.pre_map.hdb
.\..\D.psp
.\..\D.root_partition.cmp.atm
.\..\D.root_partition.cmp.dfp
.\..\D.root_partition.cmp.hdbx
.\..\D.root_partition.cmp.logdb
.\..\D.root_partition.cmp.rcf
.\..\D.root_partition.map.atm
.\..\D.root_partition.map.hdbx
.\..\D.root_partition.map.info
.\..\D.rtlv.hdb
.\..\D.rtlv_sg.cdb
.\..\D.rtlv_sg_swap.cdb
.\..\D.sgdiff.cdb
.\..\D.sgdiff.hdb
.\..\D.signalprobe.cdb
.\..\D.sim.cvwf
.\..\D.sim.hdb
.\..\D.sim.qmsg
.\..\D.sim.rdb
.\..\D.simfam
.\..\D.sld_design_entry.sci
.\..\D.sld_design_entry_dsc.sci
.\..\D.syn_hier_info
.\..\D.tan.qmsg
.\..\D.tis_db_list.ddb
.\..\D.tmw_info
.\..\prev_cmp_D.qmsg
.\..\prev_cmp_D.sim.qmsg
.\..\wed.wsf

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