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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
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Introduction - If you have any usage issues, please Google them yourself
Below the most commonly used CRC-16 as an example to illustrate the generation process. CRC-16 yards by two-bytes at the beginning of every one of the CRC register is preset to 1, then the CRC register with the 8-bit data XOR (exclusive or: the same as the binary operation 0, different 1 0 ^ 0 = 0 0 ^ 1 = 1 1 ^ 0 = 1 1 ^ 1 = 0), After the shift the CRC register from highest to lowest, the most significant bit (MSB) position zeros, the least significant bit (LSB after the shift has been out of the CRC register) 1, put the register with pre-defined item code different, or, otherwise, if the LSB is zero, you do not need to XOR. Repeat the above the descending order of the shift eight times, the first 8-bit data processing is completed, such as previous data like 8 times shift the CRC register values ​ ​ and the next 8-bit data XOR and . After completion of all the characters deal with the value of the CRC register is the final CRC value.
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