FPGA(xilinx)test bos program1 ADC

Adc\DualPort256X320X3.ngc
...\InterfaceModeHost.ngc
...\maindemoadc.bgn
...\maindemoadc.bit
...\MainDemoAdc.bld
...\MainDemoAdc.cmd_log
...\maindemoadc.drc
...\MainDemoAdc.lso
...\MainDemoAdc.ncd
...\MainDemoAdc.ngc
...\MainDemoAdc.ngd
...\MainDemoAdc.ngr
...\MainDemoAdc.pad
...\MainDemoAdc.par
...\MainDemoAdc.pcf
...\MainDemoAdc.prj
...\MainDemoAdc.ptwx
...\MainDemoAdc.stx
...\MainDemoAdc.syr
...\MainDemoAdc.twr
...\MainDemoAdc.twx
...\MainDemoAdc.unroutes
...\MainDemoAdc.ut
...\MainDemoAdc.xpi
...\MainDemoAdc.xst
...\MainDemoAdc_guide.ncd
...\MainDemoAdc_map.map
...\MainDemoAdc_map.mrp
...\MainDemoAdc_map.ncd
...\MainDemoAdc_map.ngm
...\MainDemoAdc_map.xrpt
...\MainDemoAdc_ngdbuild.xrpt
...\MainDemoAdc_pad.csv
...\MainDemoAdc_pad.txt
...\MainDemoAdc_par.xrpt
...\MainDemoAdc_prev_built.ngd
...\MainDemoAdc_summary.html
...\MainDemoAdc_summary.xml
...\MainDemoAdc_usage.xml
...\MainDemoAdc_vhdl.prj
...\MainDemoAdc_xst.xrpt
...\pDemoAdc.gise
...\pDemoAdc.ise
...\pDemoAdc.ntrc_log
...\pDemoAdc.xise
...\........_xdb\cst.xbcd
...\............\tmp\ise\version
...\............\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
...\............\...\...\............\..................\.........\HDProject_StrTbl
...\............\...\...\............\..................\__stored_object_table__
...\............\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
...\............\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...\............\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
...\............\...\...\............\................\................\dpm_project_main_StrTbl
...\............\...\...\............\................Gui\CSourceProcessView
...\............\...\...\............\...................\CSourceProcessView_StrTbl
...\............\...\...\............\...................\CViewSelector
...\............\...\...\............\...................\CViewSelector_StrTbl
...\............\...\...\............\...................\File-SynthesisOnly
...\............\...\...\............\...................\File-SynthesisOnly_StrTbl
...\............\...\...\............\...................\Library-SynthesisOnly
...\............\...\...\............\...................\Library-SynthesisOnly_StrTbl
...\............\...\...\............\...................\Process-SynthesisOnly-
...\............\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE
...\............\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE_StrTbl
...\............\...\...\............\...................\Process-SynthesisOnly-_StrTbl
...\............\...\...\............\...................\Source-SynthesisOnly-AutoCompile
...\............\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl
...\............\...\...\............\xreport\Gc_RvReportViewer-Current-Module
...\............\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
...\............\...\...\............\.......\Gc_RvReportViewer-Module-Data-MainDemoAdc
...\............\...\...\............\.......\Gc_RvReportViewer-Module-Data-MainDemoAdc_StrTbl
...\............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
...\............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
...\............\...\...\..REGISTRY__\Autonym\regkeys
...\............\...\...\............\bitgen\regkeys
...\............\...\...\............\...init\regkeys
...\............\...\...\............\common\regkeys
...\............\...\...\............\.pldfit\regkeys
...\............\...\...\............\dumpngdio\regkeys
...\............\...\...\............\fuse\regkeys
...\............\...\...\............\HierarchicalDesign\HDProject\regkeys
...\............\...\...\............\..................\regkeys
...\............\...\...\............\hprep6\regkeys
...\............\...\...\............\idem\regkeys
...\............\...\...\............\libgen\regkeys
...\............\...\...\..........

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