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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 2kb
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- Author ：叶***
- About ： Nobody
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Introduction - If you have any usage issues, please Google them yourself
Parity, eight binary data and its parity bit input calibration, and output the correct parity bit.
Packet file list
(Preview for download)
17_parity.vhd
17_test_bench.vhd
17_test_bench.vhd
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