a vga verilog language program is a vga display program, the Quartus II 9.1 to write

vga\db\logic_util_heursitic.dat
...\..\prev_cmp_vga.qmsg
...\..\prev_cmp_vga_top.asm.qmsg
...\..\prev_cmp_vga_top.fit.qmsg
...\..\prev_cmp_vga_top.map.qmsg
...\..\prev_cmp_vga_top.tan.qmsg
...\..\vga_top.asm.qmsg
...\..\vga_top.asm.rdb
...\..\vga_top.asm_labs.ddb
...\..\vga_top.cbx.xml
...\..\vga_top.cmp.cdb
...\..\vga_top.cmp.hdb
...\..\vga_top.cmp.kpt
...\..\vga_top.cmp.logdb
...\..\vga_top.cmp.rdb
...\..\vga_top.cmp.tdb
...\..\vga_top.cmp0.ddb
...\..\vga_top.db_info
...\..\vga_top.eco.cdb
...\..\vga_top.fit.qmsg
...\..\vga_top.hier_info
...\..\vga_top.hif
...\..\vga_top.lpc.html
...\..\vga_top.lpc.rdb
...\..\vga_top.lpc.txt
...\..\vga_top.map.cdb
...\..\vga_top.map.hdb
...\..\vga_top.map.logdb
...\..\vga_top.map.qmsg
...\..\vga_top.pre_map.cdb
...\..\vga_top.pre_map.hdb
...\..\vga_top.rtlv.hdb
...\..\vga_top.rtlv_sg.cdb
...\..\vga_top.rtlv_sg_swap.cdb
...\..\vga_top.sgdiff.cdb
...\..\vga_top.sgdiff.hdb
...\..\vga_top.sld_design_entry.sci
...\..\vga_top.sld_design_entry_dsc.sci
...\..\vga_top.smart_action.txt
...\..\vga_top.syn_hier_info
...\..\vga_top.tan.qmsg
...\..\vga_top.tis_db_list.ddb
...\..\vga_top.tmw_info
...\incremental_db\compiled_partitions\vga_top.root_partition.map.kpt
...\..............\README
...\rom_vga_top.mif
...\rom_vga_top.v
...\vga.qpf
...\vga.qws
...\vga_top.asm.rpt
...\vga_top.done
...\vga_top.fit.rpt
...\vga_top.fit.smsg
...\vga_top.fit.summary
...\vga_top.flow.rpt
...\vga_top.map.rpt
...\vga_top.map.summary
...\vga_top.pin
...\vga_top.pof
...\vga_top.qsf
...\vga_top.tan.rpt
...\vga_top.tan.summary
...\vga_top.v
...\vga_top.v.bak
...\incremental_db\compiled_partitions
...\db
...\incremental_db
vga

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