niosii-triple-speed-ethernet-3c120-v10-1\.sopc_builder\filters.xml
........................................\.............\install2.ptf
........................................\.............\preferences.xml
........................................\altera_avalon_half_rate_bridge.v
........................................\altera_avalon_half_rate_bridge_constraints.sdc
........................................\...memphy-library\auk_ddr_hp_controller.ocp
........................................\alt_ddrx_addr_cmd.v
........................................\alt_ddrx_afi_block.v
........................................\alt_ddrx_avalon_if.v
........................................\alt_ddrx_bank_timer.v
........................................\alt_ddrx_bank_timer_info.v
........................................\alt_ddrx_bank_timer_wrapper.v
........................................\alt_ddrx_bypass.v
........................................\alt_ddrx_cache.v
........................................\alt_ddrx_clock_and_reset.v
........................................\alt_ddrx_cmd_gen.v
........................................\alt_ddrx_cmd_queue.v
........................................\alt_ddrx_controller.v
........................................\alt_ddrx_csr.v
........................................\alt_ddrx_ddr2_odt_gen.v
........................................\alt_ddrx_ddr3_odt_gen.v
........................................\alt_ddrx_decoder.v
........................................\alt_ddrx_decoder_40.v
........................................\alt_ddrx_decoder_72.v
........................................\alt_ddrx_ecc.v
........................................\alt_ddrx_encoder.v
........................................\alt_ddrx_encoder_40.v
........................................\alt_ddrx_encoder_72.v
........................................\alt_ddrx_input_if.v
........................................\alt_ddrx_odt_gen.v
........................................\alt_ddrx_rank_monitor.v
........................................\alt_ddrx_state_machine.v
........................................\alt_ddrx_timing_param.v
........................................\alt_ddrx_wdata_fifo.v
........................................\alt_mem_phy_defines.v
........................................\button_pio.v
........................................\ccb_cpu_to_flash.v
........................................\ccb_cpu_to_io.v
........................................\ccb_dma_to_ddr2.v
........................................\cpu.ocp
........................................\cpu.sdc
........................................\cpu.v
........................................\cpu_bht_ram.mif
........................................\cpu_dc_tag_ram.mif
........................................\cpu_ic_tag_ram.mif
........................................\cpu_jtag_debug_module_sysclk.v
........................................\cpu_jtag_debug_module_tck.v
........................................\cpu_jtag_debug_module_wrapper.v
........................................\cpu_mult_cell.v
........................................\cpu_ociram_default_contents.mif
........................................\cpu_oci_test_bench.v
........................................\cpu_rf_ram_a.mif
........................................\cpu_rf_ram_b.mif
........................................\cpu_test_bench.v
........................................\db\sopcb_tb2_tserd_3c120_sopc.xml
........................................\..\tserd_3c120.db_info
........................................\..\tserd_3c120.sld_design_entry.sci
........................................\ddr2_bot.html
........................................\ddr2_bot.ppf
........................................\ddr2_bot.qip
........................................\ddr2_bot.v
........................................\ddr2_bot_advisor.ipa
........................................\ddr2_bot_alt_ddrx_controller_wrapper.v
........................................\ddr2_bot_controller_phy.v
........................................\ddr2_bot_exa