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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2012-12-07
- Size : 185kb
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- Author ：张***
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VHDL design of the 14-order FIR filter design, according to the filter coefficients as well as the verification process has been given the EP2S60F484C3 selected Altera devices.
Packet file list
(Preview for download)
FIR\image\FIR_RTL.jpg
...\sim\datain.m
...\...\fir.m
...\...\firout.m
...\...\fir_ex.v
...\...\fir_in.salt
...\...\fir_out.txt
...\...\tb_filter_ex1.v
project4.rar
FIR\image
...\sim
FIR
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