Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: VHDL_FIR Download
 Description: VHDL design of the 14-order FIR filter design, according to the filter coefficients as well as the verification process has been given the EP2S60F484C3 selected Altera devices.
 Downloaders recently: [More information of uploader 张雷]
 To Search:
File list (Check if you may need any files):
 

FIR\image\FIR_RTL.jpg
...\sim\datain.m
...\...\fir.m
...\...\firout.m
...\...\fir_ex.v
...\...\fir_in.salt
...\...\fir_out.txt
...\...\tb_filter_ex1.v
project4.rar
FIR\image
...\sim
FIR
    

CodeBus www.codebus.net