verilog i2c protocol from the machine

I2C\design\I2CSlave.prd
...\......\I2CSlave.prj
...\......\I2Cslave.v
...\......\myram.v
...\......\rev_1\.recordref
...\......\.....\AutoConstraint_I2Cslave.sdc
...\......\.....\AutoConstraint_myRAM.sdc
...\......\.....\I2Cslave.edf
...\......\.....\I2Cslave.fse
...\......\.....\I2Cslave.htm
...\......\.....\I2Cslave.ncf
...\......\.....\I2Cslave.srd
...\......\.....\I2Cslave.srm
...\......\.....\I2Cslave.srr
...\......\.....\I2Cslave.srs
...\......\.....\I2Cslave.tlg
...\......\.....\myram.edf
...\......\.....\myram.fse
...\......\.....\myram.htm
...\......\.....\myram.ncf
...\......\.....\myram.srd
...\......\.....\myram.srm
...\......\.....\myram.srr
...\......\.....\myram.srs
...\......\.....\myram.tlg
...\......\.....\rpt_I2Cslave.areasrr
...\......\.....\rpt_I2Cslave_areasrr.htm
...\......\.....\rpt_myRAM.areasrr
...\......\.....\rpt_myRAM_areasrr.htm
...\......\.....\rpt_slave_top.areasrr
...\......\.....\rpt_slave_top_areasrr.htm
...\......\.....\slave_top.edf
...\......\.....\slave_top.fse
...\......\.....\slave_top.htm
...\......\.....\slave_top.ncf
...\......\.....\slave_top.srd
...\......\.....\slave_top.srm
...\......\.....\slave_top.srr
...\......\.....\slave_top.srs
...\......\.....\slave_top.tlg
...\......\.....\.yntmp\I2Cslave.msg
...\......\.....\......\I2Cslave.plg
...\......\.....\......\I2Cslave_flink.htm
...\......\.....\......\I2Cslave_srr.htm
...\......\.....\......\I2Cslave_toc.htm
...\......\.....\......\myram.msg
...\......\.....\......\myram.plg
...\......\.....\......\myram_flink.htm
...\......\.....\......\myram_srr.htm
...\......\.....\......\myram_toc.htm
...\......\.....\......\slave_top.msg
...\......\.....\......\slave_top.plg
...\......\.....\......\slave_top_flink.htm
...\......\.....\......\slave_top_srr.htm
...\......\.....\......\slave_top_toc.htm
...\......\.....\......\timescale_flink.htm
...\......\.....\......\timescale_srr.htm
...\......\.....\......\timescale_toc.htm
...\......\.....\syntmp
...\......\.....\timescale.htm
...\......\.....\timescale.srr
...\......\.....\traplog.tlg
...\......\.....\verif\I2Cslave.vif
...\......\.....\.....\myram.vif
...\......\.....\.....\slave_top.vif
...\......\.....\verif
...\......\rev_1
...\......\sim\all.do
...\......\...\i2c_master_bit_ctrl.v
...\......\...\i2c_master_byte_ctrl.v
...\......\...\i2c_master_defines.v
...\......\...\i2c_master_top.v
...\......\...\Sim_Behav.bat
...\......\...\timescale.v
...\......\...\transcript
...\......\...\tst_bench_top.v
...\......\...\vish_stacktrace.vstf
...\......\...\vsim.wlf
...\......\...\wb_master_model.v
...\......\...\.ork\@i2@cslave\verilog.asm
...\......\...\....\..........\_primary.dat
...\......\...\....\..........\_primary.vhd
...\......\...\....\@i2@cslave
...\......\...\....\i2c_master_bit_ctrl\verilog.asm
...\......\...\....\...................\_primary.dat
...\......\...\....\...................\_primary.vhd
...\......\...\....\i2c_master_bit_ctrl
...\......\...\....\............yte_ctrl\verilog.asm
...\......\...\....\....................\_primary.dat
...\......\...\....\....................\_primary.vhd
...\......\...\....\i2c_master_byte_ctrl
...\......\...\....\...........top\verilog.asm
...\......\...\....\..............\_primary.dat
...\......\...\....\..............\_primary.vhd
...\......\...\....\i2c_master_top
...\......\...\....\my@r@a@m\verilog.asm
...\......\...\....\........\_primary.dat
...\......\...\....\........\_primary.vhd
...\......\...\....\my@r@a@m
...\......\...\....\tst_bench_top\verilog.asm

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