After the clock multiplier, through Modelsim simulation arbitrary variable duty cycle PWM signal

sim\glbl.v
...\pwm_div.cr.mti
...\pwm_div.mpf
...\pwm_div.v
...\pwm_div.v.bak
...\rom16.mif
...\rom16.v
...\tb.v
...\transcript
...\vsim.wlf
...\wave.do
...\.ork\@p@w@m_div\verilog.asm
...\....\..........\verilog.rw
...\....\..........\_primary.dat
...\....\..........\_primary.dbs
...\....\..........\_primary.vhd
...\....\glbl\verilog.asm
...\....\....\verilog.rw
...\....\....\_primary.dat
...\....\....\_primary.dbs
...\....\....\_primary.vhd
...\....\rom16\verilog.asm
...\....\.....\verilog.rw
...\....\.....\_primary.dat
...\....\.....\_primary.dbs
...\....\.....\_primary.vhd
...\....\tb\verilog.asm
...\....\..\verilog.rw
...\....\..\_primary.dat
...\....\..\_primary.dbs
...\....\..\_primary.vhd
...\....\_info
...\....\_vmake
...\....\@p@w@m_div
...\....\glbl
...\....\rom16
...\....\tb
...\....\_temp
...\work
sim

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