FPGA-based single-precision floating-point multiplier design, design of an FPGA-based single-precision floating-point multiplier. Multipliers for the five pipeline structure. Design with improved offset the redundancy Booth3 algorithm and leapfrog Wallace tree structure to reduce the number of partial product, shorten the time-consuming part of the accumulated added on the Wallace tree in the fixed-point multiplication of mantissa two false and part of the additive approach, effectively improving the processing speed and joined the special value of the processing module, and improve the function of the multiplier. Single-precision floating-point multiplier on Altera DE2 development board for verification, its maximum operating frequency of the Cyclone II EP2C35F672C6 device to 212.13 MHz.

mar2010.pdf

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