1. The source file is saved in the src directory QII project file is saved in the directory Proj 2. The functionality of the program is displayed on a VGA monitor color stripes, 8 colors, you can use the embedded logic analyzer observed signals 3. the modelsim simulation files in the proj- simulation- modelsim

S6_VGA\Src\ColorBar.bdf
......\...\ColorBar.bsf
......\...\vga_vl.v
......\Proj\cmp_state.ini
......\....\ColorBar.asm.rpt
......\....\ColorBar.cdf
......\....\ColorBar.done
......\....\ColorBar.eda.rpt
......\....\ColorBar.fit.eqn
......\....\ColorBar.fit.rpt
......\....\ColorBar.fit.summary
......\....\ColorBar.flow.rpt
......\....\ColorBar.map.eqn
......\....\ColorBar.map.rpt
......\....\ColorBar.map.summary
......\....\ColorBar.pin
......\....\ColorBar.pof
......\....\ColorBar.qpf
......\....\ColorBar.qsf
......\....\ColorBar.qws
......\....\ColorBar.sof
......\....\ColorBar.tan.rpt
......\....\ColorBar.tan.summary
......\....\ColorBar_assignment_defaults.qdf
......\....\stp1.stp
......\....\VGA_PLL.bsf
......\....\VGA_PLL.v
......\....\VGA_PLL_bb.v
......\....\vga_vl.bsf
......\....\simulation\modelsim\ColorBar.vo
......\....\..........\........\ColorBar_modelsim.xrf
......\....\..........\........\ColorBar_v.sdo
......\....\..........\........\cyclone_atoms.v
......\....\..........\........\vga_test.cr.mti
......\....\..........\........\vga_test.mpf
......\....\..........\........\vga_test.v
......\....\..........\........\vga_vl.v
......\....\..........\........\vsim.wlf
......\....\..........\........\wave.do
......\....\..........\........\.ork\_info
......\....\..........\........\....\vga_vl\verilog.asm
......\....\..........\........\....\......\_primary.dat
......\....\..........\........\....\......\_primary.vhd
......\....\..........\........\....\....test\verilog.asm
......\....\..........\........\....\........\_primary.dat
......\....\..........\........\....\........\_primary.vhd
......\....\..........\........\....\cyclone_scale_cntr\verilog.asm
......\....\..........\........\....\..................\_primary.dat
......\....\..........\........\....\..................\_primary.vhd
......\....\..........\........\....\........routing_wire\verilog.asm
......\....\..........\........\....\....................\_primary.dat
......\....\..........\........\....\....................\_primary.vhd
......\....\..........\........\....\.........am_register\verilog.asm
......\....\..........\........\....\....................\_primary.dat
......\....\..........\........\....\....................\_primary.vhd
......\....\..........\........\....\............pulse_generator\verilog.asm
......\....\..........\........\....\...........................\_primary.dat
......\....\..........\........\....\...........................\_primary.vhd
......\....\..........\........\....\............block\verilog.asm
......\....\..........\........\....\.................\_primary.dat
......\....\..........\........\....\.................\_primary.vhd
......\....\..........\........\....\........pll_reg\verilog.asm
......\....\..........\........\....\...............\_primary.dat
......\....\..........\........\....\...............\_primary.vhd
......\....\..........\........\....\...........\verilog.asm
......\....\..........\........\....\...........\_primary.dat
......\....\..........\........\....\...........\_primary.vhd
......\....\..........\........\....\........n_cntr\verilog.asm
......\....\..........\........\....\..............\_primary.dat
......\....\..........\........\....\..............\_primary.vhd
......\....\..........\........\....\.........mux21\verilog.asm
......\....\..........\........\....\..............\_primary.dat
......\....\..........\........\....\..............\_primary.vhd
......\....\..........\........\....\........m_cntr\verilog.asm
......\....\..........\........\....\..............\_primary.dat
......\....\..........\........\....\..............\_primary.vhd
......\....\..........\........\....\.........ux41\verilog.asm
......\....\..........\........\....\.............\_primary.dat
......\....\..........\........\....\.............\_primary.vhd
......\....\..........\........\....\...........21\verilog.asm
......\....\..........\........\....\.............\_primary.dat
......\....\..........\........\....\.............\_primary.vhd
......\....\..........\........\....\........lcell_re

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