Description: This routine tests the use of the independent watchdog. When the program is running, will be displayed on the LCD screen: The STM32F10x DEMO the IWDG, the TEST accordance with 250ms periodic update the IWDG counter, each update by using the SysTick L1 flashes once. Using an external interrupt to simulate a software failure, the K1 will produce an external interrupt 7, because the external interrupt priority level higher than the EWI priority, so will cause the SysTick interrupt no response, the IWDG, the counter is not overloaded, will appear Reset event K5 to reset the program after a reset occurs, L3 is lit.
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File list (Check if you may need any files):
IWDG\IWDG.opt.bak
....\IWDG.Uv2.bak
....\IWDG.uvopt
....\IWDG.uvproj
....\IWDG_uvopt.bak
....\LCD.c
....\LCD.h
....\main.c
....\output\release.plg
....\......\release.sct
....\......\release.tra
....\readme.txt
....\stm32f10x_conf.h
....\stm32f10x_it.c
....\stm32f10x_it.h
....\output
IWDG
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