FPGA implementation of the design of the elevator, verilog achieved.

LAB 15\.sopc_builder\install.ptf
......\clk_div.bsf
......\clk_div.v
......\db\design.asm.qmsg
......\..\design.asm_labs.ddb
......\..\design.cbx.xml
......\..\design.cmp.cdb
......\..\design.cmp.hdb
......\..\design.cmp.logdb
......\..\design.cmp.rdb
......\..\design.cmp.tdb
......\..\design.cmp0.ddb
......\..\design.cmp2.ddb
......\..\design.db_info
......\..\design.eco.cdb
......\..\design.fit.qmsg
......\..\design.hier_info
......\..\design.hif
......\..\design.map.cdb
......\..\design.map.hdb
......\..\design.map.logdb
......\..\design.map.qmsg
......\..\design.pre_map.cdb
......\..\design.pre_map.hdb
......\..\design.rtlv.hdb
......\..\design.rtlv_sg.cdb
......\..\design.rtlv_sg_swap.cdb
......\..\design.sgdiff.cdb
......\..\design.sgdiff.hdb
......\..\design.signalprobe.cdb
......\..\design.sim.vwf
......\..\design.sld_design_entry.sci
......\..\design.sld_design_entry_dsc.sci
......\..\design.smp_dump.txt
......\..\design.syn_hier_info
......\..\design.tan.qmsg
......\..\design.tis_db_list.ddb
......\..\design.tmw_info
......\..\mux_0kc.tdf
......\..\prev_cmp_design.asm.qmsg
......\..\prev_cmp_design.fit.qmsg
......\..\prev_cmp_design.map.qmsg
......\..\prev_cmp_design.qmsg
......\..\prev_cmp_design.tan.qmsg
......\..\wed.zsf
......\design.asm.rpt
......\design.bdf
......\design.cdf
......\design.done
......\design.dpf
......\design.fit.rpt
......\design.fit.smsg
......\design.fit.summary
......\design.flow.rpt
......\design.map.rpt
......\design.map.summary
......\design.pin
......\design.pof
......\design.qpf
......\design.qsf
......\design.sim.rpt
......\design.sim.vwf
......\design.sof
......\design.tan.rpt
......\design.tan.summary
......\design.vwf
......\design_assignment_defaults.qdf
......\lift.v
......\lift_3.bsf
......\lift_3.v
......\sopc_builder_debug_log.txt
......\.sopc_builder
......\db
LAB 15

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