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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2013-03-12
- Size : 13kb
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- Author ：huya*****
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Introduction - If you have any usage issues, please Google them yourself
A based Quartus procedure, the main function is four, but also contains a buzzer. Using VHDL language, experimental on in EP2C5T144C8 board.
Packet file list
(Preview for download)
EP1_MUX41\CNT.bsf
.........\CNT.v
.........\MUX41a.bsf
.........\MUX41a.v
.........\MUX41B.bdf
.........\MUX41B.done
.........\MUX41B.fit.smsg
.........\MUX41B.fit.summary
.........\MUX41B.map.summary
.........\MUX41B.pin
.........\MUX41B.qpf
.........\MUX41B.qsf
.........\MUX41B.qws
.........\MUX41B.sof
.........\MUX41B.sta.summary
.........\MUX41B.tan.summary
EP1_MUX41
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