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clk_div_50

  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-06-29
  • Size : 352kb
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Introduction - If you have any usage issues, please Google them yourself
a kind of frequently used frequency divider as the divider factor is 50 in the code, you can change it as your wish.
Packet file list
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clk_div_50\my_clk_div_50.qpf
..........\my_clk_div_50_top.qsf
..........\db\my_clk_div_50_top.db_info
..........\..\my_clk_div_50_top.cmp.rdb
..........\..\my_clk_div_50_top.rtlv_sg_swap.cdb
..........\..\my_clk_div_50_top.lpc.txt
..........\..\my_clk_div_50_top.rtlv.hdb
..........\..\my_clk_div_50_top.lpc.html
..........\..\my_clk_div_50_top.lpc.rdb
..........\..\my_clk_div_50_top.pre_map.cdb
..........\..\my_clk_div_50.map_bb.logdb
..........\..\my_clk_div_50_top.sgdiff.cdb
..........\..\my_clk_div_50_top.sgdiff.hdb
..........\..\my_clk_div_50_top.sld_design_entry_dsc.sci
..........\..\my_clk_div_50_top.fit.qmsg
..........\..\my_clk_div_50_top.map.cdb
..........\..\logic_util_heursitic.dat
..........\..\my_clk_div_50_top.amm.cdb
..........\..\my_clk_div_50_top.rtlv_sg.cdb
..........\..\my_clk_div_50_top.cbx.xml
..........\..\my_clk_div_50_top.hif
..........\..\my_clk_div_50_top.smart_action.txt
..........\..\my_clk_div_50_top.asm.qmsg
..........\..\my_clk_div_50_top.sta.qmsg
..........\..\my_clk_div_50_top.asm.rdb
..........\..\my_clk_div_50_top.map.hdb
..........\..\my_clk_div_50_top.cmp.logdb
..........\..\my_clk_div_50_top.cmp0.ddb
..........\..\my_clk_div_50_top.cmp2.ddb
..........\..\my_clk_div_50_top.pre_map.hdb
..........\..\my_clk_div_50_top.cmp.cdb
..........\..\my_clk_div_50_top.sta_cmp.8_slow.tdb
..........\..\my_clk_div_50_top.map.bpm
..........\..\my_clk_div_50_top.cmp1.ddb
..........\..\my_clk_div_50_top.map_bb.cdb
..........\..\my_clk_div_50_top.tis_db_list.ddb
..........\..\my_clk_div_50_top.map_bb.hdb
..........\..\my_clk_div_50_top.idb.cdb
..........\..\my_clk_div_50_top.cmp.hdb
..........\..\my_clk_div_50_top.sta.rdb
..........\..\my_clk_div_50_top.asm_labs.ddb
..........\..\my_clk_div_50_top.eda.qmsg
..........\..\my_clk_div_50_top.rpp.qmsg
..........\..\my_clk_div_50_top.hier_info
..........\..\my_clk_div_50_top.sgate.rvd
..........\..\my_clk_div_50_top.sgate_sm.rvd
..........\..\prev_cmp_my_clk_div_50.qmsg
..........\..\my_clk_div_50_top.map.qmsg
..........\..\my_clk_div_50_top.sld_design_entry.sci
..........\..\my_clk_div_50_top.cmp.bpm
..........\..\my_clk_div_50_top.syn_hier_info
..........\..\my_clk_div_50_top.map.kpt
..........\..\my_clk_div_50_top.cmp_merge.kpt
..........\..\my_clk_div_50_top.cmp.kpt
..........\my_clk_div_50_top.map.summary
..........\incremental_db\compiled_partitions\my_clk_div_50_top.db_info
..........\..............\...................\my_clk_div_50_top.root_partition.map.kpt
..........\..............\...................\my_clk_div_50_top.root_partition.map.hbdb.hb_info
..........\..............\...................\my_clk_div_50_top.root_partition.map.hbdb.sig
..........\..............\...................\my_clk_div_50_top.root_partition.cmp.logdb
..........\..............\...................\my_clk_div_50_top.root_partition.cmp.kpt
..........\..............\...................\my_clk_div_50_top.root_partition.map.dpi
..........\..............\...................\my_clk_div_50_top.root_partition.map.cdb
..........\..............\...................\my_clk_div_50_top.root_partition.map.hdb
..........\..............\...................\my_clk_div_50_top.root_partition.map.hbdb.cdb
..........\..............\...................\my_clk_div_50_top.root_partition.map.hbdb.hdb
..........\..............\...................\my_clk_div_50_top.root_partition.cmp.rcfdb
..........\..............\...................\my_clk_div_50_top.root_partition.cmp.cdb
..........\..............\...................\my_clk_div_50_top.root_partition.cmp.hdb
..........\..............\...................\my_clk_div_50_top.root_partition.cmp.dfp
..........\..............\README
..........\my_clk_div_50_top.pin
..........\my_clk_div_50_top.fit.smsg
..........\my_clk_div_50_top.fit.summary
..........\my_clk_div_50_top.sof
..........\my_clk_div_50_top.pof
..........\my_clk_div_50_top.done
..........\my_clk_div_50_top_nativelink_simulation.rpt
..........\simulation\modelsim\my_clk_div_50_top.vt
..........\..........\........\my_clk_div_50_top_modelsim.xrf
..........\..........\........\my_clk_div_50_top.
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