FPGA-based tablets did not ram read and write function code can be written and read out the 16bit data, suitable for beginners to learn and imitate Use

ram00\asynram.asm.rpt
.....\asynram.done
.....\asynram.fit.eqn
.....\asynram.fit.rpt
.....\asynram.fit.summary
.....\asynram.flow.rpt
.....\asynram.map.eqn
.....\asynram.map.rpt
.....\asynram.map.summary
.....\asynram.pin
.....\asynram.pof
.....\asynram.qpf
.....\asynram.qsf
.....\asynram.qws
.....\asynram.sim.rpt
.....\asynram.sof
.....\asynram.tan.rpt
.....\asynram.tan.summary
.....\asynram.vhd
.....\asynram.vwf
.....\asynram_assignment_defaults.qdf
.....\cmp_state.ini
.....\db\asynram.asm.qmsg
.....\..\asynram.cbx.xml
.....\..\asynram.cmp.cdb
.....\..\asynram.cmp.hdb
.....\..\asynram.cmp.qrpt
.....\..\asynram.cmp.rdb
.....\..\asynram.cmp.tdb
.....\..\asynram.cmp0.ddb
.....\..\asynram.dbp
.....\..\asynram.db_info
.....\..\asynram.eco.cdb
.....\..\asynram.eds_overflow
.....\..\asynram.fit.qmsg
.....\..\asynram.fnsim.cdb
.....\..\asynram.fnsim.hdb
.....\..\asynram.fnsim.qmsg
.....\..\asynram.hier_info
.....\..\asynram.hif
.....\..\asynram.map.cdb
.....\..\asynram.map.hdb
.....\..\asynram.map.qmsg
.....\..\asynram.pre_map.cdb
.....\..\asynram.pre_map.hdb
.....\..\asynram.psp
.....\..\asynram.rtlv.hdb
.....\..\asynram.rtlv_sg.cdb
.....\..\asynram.rtlv_sg_swap.cdb
.....\..\asynram.sgdiff.cdb
.....\..\asynram.sgdiff.hdb
.....\..\asynram.sim.hdb
.....\..\asynram.sim.qmsg
.....\..\asynram.sim.qrpt
.....\..\asynram.sim.rdb
.....\..\asynram.sim.vwf
.....\..\asynram.sld_design_entry.sci
.....\..\asynram.sld_design_entry_dsc.sci
.....\..\asynram.syn_hier_info
.....\..\asynram.tan.qmsg
.....\..\asynram_cmp.qrpt
.....\db
ram00

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