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dds_simu_v100

  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-08-29
  • Size : 378kb
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Duty cycle, amplitude, step adjustable DDS module, the board has successfully achieved
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dds_simu_v100
.............\altaccumulate0.bsf
.............\altaccumulate0.qip
.............\altaccumulate0.v
.............\altaccumulate0_wave0.jpg
.............\altaccumulate0_waveforms.html
.............\comp_phase1.bsf
.............\comp_phase1.qip
.............\comp_phase1.v
.............\comp_phase2.bsf
.............\comp_phase2.qip
.............\comp_phase2.v
.............\comp_phase3.bsf
.............\comp_phase3.qip
.............\comp_phase3.v
.............\comp_phase3_wave0.jpg
.............\comp_phase3_waveforms.html
.............\comp_stop_s8bit.bsf
.............\comp_stop_s8bit.qip
.............\comp_stop_s8bit.v
.............\db
.............\..\accum_8df.tdf
.............\..\accum_9tg.tdf
.............\..\add_sub_1fk.tdf
.............\..\add_sub_4ch.tdf
.............\..\add_sub_8ch.tdf
.............\..\add_sub_d2k.tdf
.............\..\add_sub_fgk.tdf
.............\..\cmpr_2bj.tdf
.............\..\cmpr_cfi.tdf
.............\..\cmpr_j5l.tdf
.............\..\cmpr_uig.tdf
.............\..\cntr_g3i.tdf
.............\..\cntr_g8j.tdf
.............\..\cntr_lni.tdf
.............\..\logic_util_heursitic.dat
.............\..\lpm_constant_9a4.tdf
.............\..\lpm_constant_aa4.tdf
.............\..\lpm_constant_ba4.tdf
.............\..\lpm_constant_ca4.tdf
.............\..\lpm_constant_ga4.tdf
.............\..\lpm_constant_j84.tdf
.............\..\lpm_constant_k84.tdf
.............\..\lpm_constant_l84.tdf
.............\..\lpm_constant_m84.tdf
.............\..\lpm_constant_n84.tdf
.............\..\lpm_constant_rb4.tdf
.............\..\prev_cmp_simu_dds.asm.qmsg
.............\..\prev_cmp_simu_dds.fit.qmsg
.............\..\prev_cmp_simu_dds.map.qmsg
.............\..\prev_cmp_simu_dds.qmsg
.............\..\prev_cmp_simu_dds.sim.qmsg
.............\..\prev_cmp_simu_dds.tan.qmsg
.............\..\simu_dds.db_info
.............\..\simu_dds.sim.cvwf
.............\..\simu_dds.sld_design_entry.sci
.............\..\wed.wsf
.............\dds_4phase_fixed_v100.bdf
.............\dds_4phase_fixed_v100.bsf
.............\dds_4phase_fixed_v200.bdf
.............\dds_4phase_fixed_v200.bsf
.............\dds_acc.bsf
.............\dds_acc.qip
.............\dds_acc.v
.............\dds_acc_9bit.bsf
.............\dds_acc_9bit.qip
.............\dds_acc_9bit.v
.............\dds_acc_9bit_wave0.jpg
.............\dds_acc_9bit_waveforms.html
.............\dds_acc_s8bit.bsf
.............\dds_acc_s8bit.qip
.............\dds_acc_s8bit.v
.............\dds_phase_preload_v100.bsf
.............\dds_phase_preload_v100.v
.............\dutyless20_v100.bdf
.............\dutyless20_v100.bsf
.............\greybox_tmp
.............\...........\cbx_args.txt
.............\incremental_db
.............\..............\compiled_partitions
.............\..............\...................\simu_dds.db_info
.............\..............\...................\simu_dds.root_partition.cmp.dfp
.............\..............\...................\simu_dds.root_partition.cmp.kpt
.............\..............\...................\simu_dds.root_partition.cmp.logdb
.............\..............\...................\simu_dds.root_partition.map.dpi
.............\..............\...................\simu_dds.root_partition.map.kpt
.............\..............\README
.............\lpm_mult0.bsf
.............\lpm_mult0.qip
.............\lpm_mult0.v
.............\lpm_mult0_wave0.jpg
.............\lpm_mult0_waveforms.html
.............\pcyc_comp.bsf
.............\pcyc_comp.qip
.............\pcyc_comp.v
.............\phase_cnt_s8bit.bsf
.............\phase_cnt_s8bit.qip
.............\phase_cnt_s8bit.v
.............\phase_gener_4fixed_s8bit.bdf
.............\phase_gener_4fixed_s8bit.bsf
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