Encoder 38 code, FPGA implementation, language Verilog prepared

decode38
........\Project
........\.......\db
........\.......\..\decode38.cbx.xml
........\.......\..\decode38.cmp.rdb
........\.......\..\decode38.dbp
........\.......\..\decode38.db_info
........\.......\..\decode38.eco.cdb
........\.......\..\decode38.hier_info
........\.......\..\decode38.hif
........\.......\..\decode38.map.bpm
........\.......\..\decode38.map.cdb
........\.......\..\decode38.map.ecobp
........\.......\..\decode38.map.hdb
........\.......\..\decode38.map.logdb
........\.......\..\decode38.map.qmsg
........\.......\..\decode38.map_bb.cdb
........\.......\..\decode38.map_bb.hdb
........\.......\..\decode38.map_bb.logdb
........\.......\..\decode38.pre_map.cdb
........\.......\..\decode38.pre_map.hdb
........\.......\..\decode38.psp
........\.......\..\decode38.pss
........\.......\..\decode38.rpp.qmsg
........\.......\..\decode38.rtlv.hdb
........\.......\..\decode38.rtlv_sg.cdb
........\.......\..\decode38.rtlv_sg_swap.cdb
........\.......\..\decode38.sgate.rvd
........\.......\..\decode38.sgate_sm.rvd
........\.......\..\decode38.sgdiff.cdb
........\.......\..\decode38.sgdiff.hdb
........\.......\..\decode38.sld_design_entry.sci
........\.......\..\decode38.sld_design_entry_dsc.sci
........\.......\..\decode38.syn_hier_info
........\.......\..\decode38.tis_db_list.ddb
........\.......\..\gray2bin.cbx.xml
........\.......\..\gray2bin.cmp.rdb
........\.......\..\gray2bin.dbp
........\.......\..\gray2bin.db_info
........\.......\..\gray2bin.eco.cdb
........\.......\..\gray2bin.hier_info
........\.......\..\gray2bin.hif
........\.......\..\gray2bin.map.bpm
........\.......\..\gray2bin.map.cdb
........\.......\..\gray2bin.map.ecobp
........\.......\..\gray2bin.map.hdb
........\.......\..\gray2bin.map.logdb
........\.......\..\gray2bin.map.qmsg
........\.......\..\gray2bin.map_bb.cdb
........\.......\..\gray2bin.map_bb.hdb
........\.......\..\gray2bin.map_bb.logdb
........\.......\..\gray2bin.pre_map.cdb
........\.......\..\gray2bin.pre_map.hdb
........\.......\..\gray2bin.psp
........\.......\..\gray2bin.pss
........\.......\..\gray2bin.rpp.qmsg
........\.......\..\gray2bin.rtlv.hdb
........\.......\..\gray2bin.rtlv_sg.cdb
........\.......\..\gray2bin.rtlv_sg_swap.cdb
........\.......\..\gray2bin.sgate.rvd
........\.......\..\gray2bin.sgate_sm.rvd
........\.......\..\gray2bin.sgdiff.cdb
........\.......\..\gray2bin.sgdiff.hdb
........\.......\..\gray2bin.sld_design_entry.sci
........\.......\..\gray2bin.sld_design_entry_dsc.sci
........\.......\..\gray2bin.syn_hier_info
........\.......\..\gray2bin.tis_db_list.ddb
........\.......\..\LFSR.cbx.xml
........\.......\..\LFSR.cmp.rdb
........\.......\..\LFSR.dbp
........\.......\..\LFSR.db_info
........\.......\..\LFSR.eco.cdb
........\.......\..\LFSR.hier_info
........\.......\..\LFSR.hif
........\.......\..\LFSR.map.bpm
........\.......\..\LFSR.map.cdb
........\.......\..\LFSR.map.ecobp
........\.......\..\LFSR.map.hdb
........\.......\..\LFSR.map.logdb
........\.......\..\LFSR.map.qmsg
........\.......\..\LFSR.map_bb.cdb
........\.......\..\LFSR.map_bb.hdb
........\.......\..\LFSR.map_bb.logdb
........\.......\..\LFSR.pre_map.cdb
........\.......\..\LFSR.pre_map.hdb
........\.......\..\LFSR.psp
........\.......\..\LFSR.pss
........\.......\..\LFSR.rpp.qmsg
........\.......\..\LFSR.rtlv.hdb
........\.......\..\LFSR.rtlv_sg.cdb
........\.......\..\LFSR.rtlv_sg_swap.cdb
........\.......\..\LFSR.sgate.rvd
........\.......\..\LFSR.sgate_sm.rvd
........\.......\..\LFSR.sgdiff.cdb
........\.......\..\LFSR.sgdiff.hdb
........\.......\..\LFSR.sld_design_entry.sci
........\.......\..\LFSR.sld_design_entry_dsc.sci
........\.......\..\LFSR.syn_hier_info
........\.......\..\LFSR.tis_db_list.ddb
........\.......\..\prev_cmp_decode38.map.qmsg

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