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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2013-10-04
- Size : 9kb
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- Author ：W****
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Introduction - If you have any usage issues, please Google them yourself
This is a binary to BCD convert designed by using the “shift and add-3 algorithm”. The verilog code of basic cell add-3 is also included in this file.
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Binary_to_BCD_Converter.docx
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