Electronic clock, alarm clock, stopwatch, adjustable time, the use of six digital tube display

Verilog_COMPLEXCLOCK v2013.10.07\db\MyVerilogProject.asm.qmsg
................................\..\MyVerilogProject.cbx.xml
................................\..\MyVerilogProject.cmp.bpm
................................\..\MyVerilogProject.cmp.cdb
................................\..\MyVerilogProject.cmp.ecobp
................................\..\MyVerilogProject.cmp.hdb
................................\..\MyVerilogProject.cmp.kpt
................................\..\MyVerilogProject.cmp.logdb
................................\..\MyVerilogProject.cmp.rdb
................................\..\MyVerilogProject.cmp.tdb
................................\..\MyVerilogProject.cmp0.ddb
................................\..\MyVerilogProject.cmp_merge.kpt
................................\..\MyVerilogProject.db_info
................................\..\MyVerilogProject.eco.cdb
................................\..\MyVerilogProject.eda.qmsg
................................\..\MyVerilogProject.fit.qmsg
................................\..\MyVerilogProject.hier_info
................................\..\MyVerilogProject.hif
................................\..\MyVerilogProject.lpc.html
................................\..\MyVerilogProject.lpc.rdb
................................\..\MyVerilogProject.lpc.txt
................................\..\MyVerilogProject.map.bpm
................................\..\MyVerilogProject.map.cdb
................................\..\MyVerilogProject.map.ecobp
................................\..\MyVerilogProject.map.hdb
................................\..\MyVerilogProject.map.kpt
................................\..\MyVerilogProject.map.logdb
................................\..\MyVerilogProject.map.qmsg
................................\..\MyVerilogProject.map_bb.cdb
................................\..\MyVerilogProject.map_bb.hdb
................................\..\MyVerilogProject.map_bb.logdb
................................\..\MyVerilogProject.merge.qmsg
................................\..\MyVerilogProject.pre_map.cdb
................................\..\MyVerilogProject.pre_map.hdb
................................\..\MyVerilogProject.rpp.qmsg
................................\..\MyVerilogProject.rtlv.hdb
................................\..\MyVerilogProject.rtlv_sg.cdb
................................\..\MyVerilogProject.rtlv_sg_swap.cdb
................................\..\MyVerilogProject.sgate.rvd
................................\..\MyVerilogProject.sgate_sm.rvd
................................\..\MyVerilogProject.sgdiff.cdb
................................\..\MyVerilogProject.sgdiff.hdb
................................\..\MyVerilogProject.sld_design_entry.sci
................................\..\MyVerilogProject.sld_design_entry_dsc.sci
................................\..\MyVerilogProject.smp_dump.txt
................................\..\MyVerilogProject.syn_hier_info
................................\..\MyVerilogProject.tan.qmsg
................................\..\MyVerilogProject.tis_db_list.ddb
................................\..\MyVerilogProject.tmw_info
................................\..\MyVerilogProject_global_asgn_op.abo
................................\..\prev_cmp_MyVerilogProject.asm.qmsg
................................\..\prev_cmp_MyVerilogProject.eda.qmsg
................................\..\prev_cmp_MyVerilogProject.fit.qmsg
................................\..\prev_cmp_MyVerilogProject.map.qmsg
................................\..\prev_cmp_MyVerilogProject.merge.qmsg
................................\..\prev_cmp_MyVerilogProject.qmsg
................................\..\prev_cmp_MyVerilogProject.tan.qmsg
................................\incremental_db\compiled_partitions\MyVerilogProject.root_partition.cmp.atm
................................\..............\...................\MyVerilogProject.root_partition.cmp.dfp
................................\..............\...................\MyVerilogProject.root_partition.cmp.hdbx
................................\..............\...................\MyVerilogProject.root_pa

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