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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2013-04-12
- Size : 3.07mb
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- Author ：吴***
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The UVM World official release of the source code of the UVM (Universal Verification Methodology), based on SystemVerilog for ASIC Verification. 2013-03 latest release uvm-1.1d.tar.gz
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uvm-1.1d_RC7.tar
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