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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2013-06-03
- Size : 78kb
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- Author ：李****
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Introduction - If you have any usage issues, please Google them yourself
VHDL language is a high-level language for circuit design, digital systems primarily used to describe the structure, behavior, functionality and interfaces. Its application is mainly used in digital circuit design. In the FPGA/CPLD/EPLD/ASIC design, such as defining the chip pin functions.
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Verilog_HDL设计实例.pdf
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