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shiyan_1

  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-06-12
  • Size : 480kb
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  • Author :方****
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Introduction - If you have any usage issues, please Google them yourself
This is a VHDL program, program counter input and output from count 1 to 8, to complete such a feature.
Packet file list
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shiyan_1
........\jsq
........\...\db
........\...\..\jsq.asm.qmsg
........\...\..\jsq.cbx.xml
........\...\..\jsq.cmp.bpm
........\...\..\jsq.cmp.cdb
........\...\..\jsq.cmp.ecobp
........\...\..\jsq.cmp.hdb
........\...\..\jsq.cmp.logdb
........\...\..\jsq.cmp.rdb
........\...\..\jsq.cmp.tdb
........\...\..\jsq.cmp0.ddb
........\...\..\jsq.cmp2.ddb
........\...\..\jsq.db_info
........\...\..\jsq.eco.cdb
........\...\..\jsq.eds_overflow
........\...\..\jsq.fit.qmsg
........\...\..\jsq.fnsim.cdb
........\...\..\jsq.fnsim.hdb
........\...\..\jsq.fnsim.qmsg
........\...\..\jsq.hier_info
........\...\..\jsq.hif
........\...\..\jsq.map.bpm
........\...\..\jsq.map.cdb
........\...\..\jsq.map.ecobp
........\...\..\jsq.map.hdb
........\...\..\jsq.map.logdb
........\...\..\jsq.map.qmsg
........\...\..\jsq.map_bb.cdb
........\...\..\jsq.map_bb.hdb
........\...\..\jsq.map_bb.hdbx
........\...\..\jsq.map_bb.logdb
........\...\..\jsq.pre_map.cdb
........\...\..\jsq.pre_map.hdb
........\...\..\jsq.psp
........\...\..\jsq.root_partition.cmp.atm
........\...\..\jsq.root_partition.cmp.dfp
........\...\..\jsq.root_partition.cmp.hdbx
........\...\..\jsq.root_partition.cmp.logdb
........\...\..\jsq.root_partition.cmp.rcf
........\...\..\jsq.root_partition.map.atm
........\...\..\jsq.root_partition.map.hdbx
........\...\..\jsq.root_partition.map.info
........\...\..\jsq.rtlv.hdb
........\...\..\jsq.rtlv_sg.cdb
........\...\..\jsq.rtlv_sg_swap.cdb
........\...\..\jsq.sgdiff.cdb
........\...\..\jsq.sgdiff.hdb
........\...\..\jsq.signalprobe.cdb
........\...\..\jsq.sim.cvwf
........\...\..\jsq.sim.hdb
........\...\..\jsq.sim.qmsg
........\...\..\jsq.sim.rdb
........\...\..\jsq.simfam
........\...\..\jsq.sld_design_entry.sci
........\...\..\jsq.sld_design_entry_dsc.sci
........\...\..\jsq.syn_hier_info
........\...\..\jsq.tan.qmsg
........\...\..\jsq.tis_db_list.ddb
........\...\..\jsq.tmw_info
........\...\..\prev_cmp_jsq.qmsg
........\...\..\wed.wsf
........\...\jsq.asm.rpt
........\...\jsq.bdf
........\...\jsq.done
........\...\jsq.fit.rpt
........\...\jsq.fit.smsg
........\...\jsq.fit.summary
........\...\jsq.flow.rpt
........\...\jsq.map.rpt
........\...\jsq.map.summary
........\...\jsq.pin
........\...\jsq.qpf
........\...\jsq.qsf
........\...\jsq.qws
........\...\jsq.sim.rpt
........\...\jsq.tan.rpt
........\...\jsq.tan.summary
........\...\jsq.vwf
........\led_key
........\.......\db
........\.......\..\led_key.asm.qmsg
........\.......\..\led_key.cbx.xml
........\.......\..\led_key.cmp.bpm
........\.......\..\led_key.cmp.cdb
........\.......\..\led_key.cmp.ecobp
........\.......\..\led_key.cmp.hdb
........\.......\..\led_key.cmp.logdb
........\.......\..\led_key.cmp.rdb
........\.......\..\led_key.cmp.tdb
........\.......\..\led_key.cmp0.ddb
........\.......\..\led_key.cmp2.ddb
........\.......\..\led_key.db_info
........\.......\..\led_key.eco.cdb
........\.......\..\led_key.fit.qmsg
........\.......\..\led_key.fnsim.cdb
........\.......\..\led_key.fnsim.hdb
........\.......\..\led_key.fnsim.qmsg
........\.......\..\led_key.hier_info
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